19-3022; Rev 0; 10/03
KIT
ATION
EVALU
BLE
AVAILA
15-Bit, 65Msps ADC with -78.2dBFS
Noise Floor for IF Applications
General Description
Features
o
65Msps Minimum Sampling Rate
o
-78.2dBFS Noise Floor
o
Excellent Dynamic Performance
73.6dB SNR at f
IN
= 70MHz and A
IN
= -2dBFS
88dBc/92dBc Single-Tone SFDR1/SFDR2 at
f
IN
= 70MHz and A
IN
= -2dBFS
-85dB Multitone SFDR at f
IN1
= 69MHz
and f
IN2
= 71MHz
o
Less than 0.25ps Sampling Jitter
o
Fully Differential Analog Input Voltage Range of
2.56V
P-P
o
CMOS-Compatible Two’s-Complement Data Output
o
Separate Data Valid Clock and Overrange Outputs
o
Flexible-Input Clock Buffer
o
EV Kit Available for MAX1418
(Order MAX1427EVKIT)
MAX1418
The MAX1418 is a 5V, high-speed, high-performance
analog-to-digital converter (ADC) featuring a fully differ-
ential wideband track-and-hold (T/H) and a 15-bit con-
verter core. The MAX1418 is optimized for multichannel,
multimode receivers, which require the ADC to meet very
stringent dynamic performance requirements. With a
noise floor of -78.2dBFS, the MAX1418 allows for the
design of receivers with superior sensitivity.
The MAX1418 achieves two-tone, spurious-free dynamic
range (SFDR) of -85dBc for input tones of 69MHz and
71MHz. Its excellent signal-to-noise ratio (SNR) of 73.6dB
and single-tone SFDR performance (SFDR1/SFDR2) of
88dBc/92dBc at f
IN
= 70MHz and a sampling rate of
65Msps make this part ideal for high-performance digital
receivers.
The MAX1418 operates from an analog 5V and a digital
3V supply, features a 2.56V
P-P
full-scale input range,
and allows for a sampling speed of up to 65Msps. The
input T/H operates with a -1dB full-power bandwidth of
260MHz.
The MAX1418 features parallel, CMOS-compatible out-
puts in two’s-complement format. To enable the interface
with a wide range of logic devices, this ADC provides a
separate output driver power-supply range of 2.3V to
3.5V. The MAX1418 is manufactured in an 8mm x 8mm,
56-pin QFN package with exposed paddle (EP) for low
thermal resistance, and is specified for the extended
industrial (-40°C to +85°C) temperature range.
Note that IF parts MAX1418, MAX1428, and MAX1430
(see
Pin-Compatible Higher/Lower Speed Versions
Selection
table) are recommended for applications that
require high dynamic performance for input frequen-
cies greater than f
CLK
/3. Unlike its baseband counter-
part MAX1419, the MAX1418 is optimized for input
frequencies greater than f
CLK
/3.
Ordering Information
PART
MAX1418ETN
TEMP RANGE
-40°C to +85°C
PIN-PACKAGE
56 QFN-EP*
*EP
= Exposed paddle.
Applications
Cellular Base-Station Transceiver Systems (BTS)
Wireless Local Loop (WLL)
Single- and Multicarrier Receivers
Multistandard Receivers
E911 Location Receivers
Power Amplifier Linearity Correction
Antenna Array Processing
Pin-Compatible Higher/Lower
Speed Versions Selection
PART
MAX1418
MAX1419
MAX1427
MAX1428*
MAX1429*
MAX1430*
SPEED GRADE
(Msps)
65
65
80
80
100
100
TARGET
APPLICATION
IF
Baseband
Baseband
IF
Baseband
IF
*Future
product—contact factory for availability.
Pin Configuration appears at end of data sheet.
________________________________________________________________
Maxim Integrated Products
1
For pricing, delivery, and ordering information, please contact Maxim/Dallas Direct! at
1-888-629-4642, or visit Maxim’s website at www.maxim-ic.com.
15-Bit, 65Msps ADC with -78.2dBFS
Noise Floor for IF Applications
MAX1418
ABSOLUTE MAXIMUM RATINGS
AV
CC
, DV
CC
, DRV
CC
to GND.................................. -0.3V to +6V
INP, INN, CLKP, CLKN, CM to GND........-0.3V to (AV
CC
+ 0.3V)
D0–D14, DAV, DOR to GND..................-0.3V to (DRV
CC
+ 0.3V)
Continuous Power Dissipation (T
A
= +70°C)
56-Pin QFN (derate 47.6mW/°C above +70°C) ......3809.5mW
Operating Temperature Range ...........................-40°C to +85°C
Thermal Resistance
θ
J
A
...................................................21°C/W
Junction Temperature ......................................................+150°C
Storage Temperature Range .............................-60°C to +150°C
Lead Temperature (soldering, 10s) .................................+300°C
Stresses beyond those listed under “Absolute Maximum Ratings” may cause permanent damage to the device. These are stress ratings only, and functional
operation of the device at these or any other conditions beyond those indicated in the operational sections of the specifications is not implied. Exposure to
absolute maximum rating conditions for extended periods may affect device reliability.
ELECTRICAL CHARACTERISTICS
(AV
CC
= 5V, DV
CC
= DRV
CC
= 2.5V, GND = 0, INP and INN driven differentially with -2dBFS, CLKP and CLKN driven differentially
with a 2V
P-P
sinusoidal input signal, C
L
= 5pF at digital outputs, f
CLK
= 65MHz, T
A
= T
MIN
to T
MAX
, unless otherwise noted. Typical
values are at T
A
= +25°C, unless otherwise noted.
≥+25°C
guaranteed by production test, <+25°C guaranteed by design and char-
acterization.)
PARAMETER
DC ACCURACY
Resolution
Integral Nonlinearity
Differential Nonlinearity
Offset Error
Gain Error
ANALOG INPUT (INP, INN)
Differential Input Voltage Range
Common-Mode Input Voltage
Differential Input Resistance
Differential Input Capacitance
Full-Power Analog Bandwidth
CONVERSION RATE
Maximum Clock Frequency
Minimum Clock Frequency
Aperture Jitter
CLOCK INPUT (CLKP, CLKN)
Full-Scale Differential Input
Voltage
Common-Mode Input Voltage
Differential Input Resistance
Differential Input Capacitance
DYNAMIC CHARACTERISTICS
Thermal + Quantization
Noise Floor
NF
Analog input <-35dBFS
-78.2
dBFS
V
DIFFCLK
V
CM
R
INCLK
C
INCLK
Fully differential input drive, V
CLKP
- V
CLKN
Self-biased
0.5 to
3.0
2.4
2
±15%
1
V
V
kΩ
pF
f
CLK
f
CLK
t
AJ
65
20
0.21
MHz
MHz
ps
RMS
V
DIFF
V
CM
R
IN
C
IN
FPBW
-1dB
-1dB rolloff for a full-scale input
Fully differential inputs drive, V
DIFF
= V
INP
- V
INN
Self-biased
2.56
4.17
1
±15%
1
260
V
P-P
V
kΩ
pF
MHz
INL
DNL
f
IN
= 15MHz
f
IN
= 70MHz, no missing codes guaranteed
-12
-4
15
±1.5
±0.4
+12
+4
Bits
LSB
LSB
mV
%FS
SYMBOL
CONDITIONS
MIN
TYP
MAX
UNITS
2
_______________________________________________________________________________________
15-Bit, 65Msps ADC with -78.2dBFS
Noise Floor for IF Applications
ELECTRICAL CHARACTERISTICS (continued)
(AV
CC
= 5V, DV
CC
= DRV
CC
= 2.5V, GND = 0, INP and INN driven differentially with -2dBFS, CLKP and CLKN driven differentially
with a 2V
P-P
sinusoidal input signal, C
L
= 5pF at digital outputs, f
CLK
= 65MHz, T
A
= T
MIN
to T
MAX
, unless otherwise noted. Typical
values are at T
A
= +25°C, unless otherwise noted.
≥+25°C
guaranteed by production test, <+25°C guaranteed by design and char-
acterization.)
PARAMETER
SYMBOL
CONDITIONS
f
IN
= 5MHz at -2dBFS
f
IN
= 15MHz at -2dBFS
Signal-to-Noise Ratio (Note 1)
SNR
f
IN
= 35MHz at -2dBFS
f
IN
= 70MHz at -2dBFS
f
IN
= 170MHz at -6dBFS
f
IN
= 5MHz at -2dBFS
Signal-to-Noise and Distortion
(Note 2)
f
IN
= 15MHz at -2dBFS
SINAD
f
IN
= 35MHz at -2dBFS
f
IN
= 70MHz at -2dBFS
f
IN
= 170MHz at -6dBFS
f
IN
= 5MHz at -2dBFS
Spurious-Free Dynamic Range
(HD2 and HD3)
(Note 2)
f
IN
= 15MHz at -2dBFS
SFDR1
f
IN
= 35MHz at -2dBFS
f
IN
= 70MHz at -2dBFS
f
IN
= 170MHz at -6dBFS
f
IN
= 5MHz at -2dBFS
Spurious-Free Dynamic Range
(HD4 and Higher)
(Note 2)
f
IN
= 15MHz at -2dBFS
SFDR2
f
IN
= 35MHz at -2dBFS
f
IN
= 70MHz at -2dBFS
f
IN
= 170MHz at -6dBFS
Two-Tone Intermodulation
Distortion
Two-Tone Spurious-Free
Dynamic Range
TTIMD
f
IN1
= 69MHz at -8dBFS;
f
IN2
= 71MHz at -8dBFS
f
IN1
= 69MHz at -12dBFS < f
IN1
< -100dBFS;
f
IN2
= 71MHz at -12dBFS < f
IN2
< -100dBFS
(Note 2)
84.5
78
71
72
MIN
TYP
75
75
74.8
73.6
68.5
74.8
74.8
74.4
73.3
64.4
90
90
88
88
67.5
95
95
93
92
82
-85
dBc
dBc
dBc
dB
dB
MAX
UNITS
MAX1418
SFDR
TT
-100
dBFS
DIGITAL OUTPUTS (D0–D14, DAV, DOR)
Digital Output-Voltage Low
Digital Output-Voltage High
V
OL
V
OH
DV
CC
-
0.5
0.5
V
V
TIMING CHARACTERISTICS (DV
CC
= DRV
CC
= 2.5V)
Figure 4
CLKP/CLKN Duty Cycle
Effective Aperture Delay
Output Data Delay
Data Valid Delay
Duty cycle
t
AD
t
DAT
t
DAV
(Note 3)
(Note 3)
3.0
5.3
50
±5
230
4.5
6.5
7.5
8.7
%
ps
ns
ns
_______________________________________________________________________________________
3
15-Bit, 65Msps ADC with -78.2dBFS
Noise Floor for IF Applications
MAX1418
ELECTRICAL CHARACTERISTICS (continued)
(AV
CC
= 5V, DV
CC
= DRV
CC
= 2.5V, GND = 0, INP and INN driven differentially with -2dBFS, CLKP and CLKN driven differentially
with a 2V
P-P
sinusoidal input signal, C
L
= 5pF at digital outputs, f
CLK
= 65MHz, T
A
= T
MIN
to T
MAX
, unless otherwise noted. Typical
values are at T
A
= +25°C, unless otherwise noted.
≥+25°C
guaranteed by production test, <+25°C guaranteed by design and char-
acterization.)
PARAMETER
Pipeline Latency
CLKP Rising Edge to DATA
Not Valid
CLKP Rising Edge to DATA
Valid (Guaranteed)
DATA Setup Time
(Before DAV Rising Edge)
DATA Hold Time
(After DAV Rising Edge)
SYMBOL
t
LATENCY
t
DNV
t
DGV
t
SETUP
t
HOLD
(Note 3)
(Note 3)
(Note 3)
(Note 3)
2.6
3.4
t
CLKP
-
0.5
CONDITIONS
MIN
TYP
3
3.8
5.2
t
CLKP
+ 1.3
5.7
8.6
t
CLKP
+ 2.4
MAX
UNITS
Clock
cycles
ns
ns
ns
ns
t
CLKN
- t
CLKN
- t
CLKN
-
3.6
2.8
2.0
TIMING CHARACTERISTICS (DV
CC
= DRV
CC
= 3.3V)
Figure 4
CLKP/CLKN Duty Cycle
Effective Aperture Delay
Output Data Delay
Data Valid Delay
Pipeline Latency
CLKP Rising Edge to
DATA Not Valid
CLKP Rising Edge to
DATA Valid (Guaranteed)
DATA Setup Time
(Before DAV Rising Edge)
DATA Hold Time
(After DAV Rising Edge)
POWER REQUIREMENTS
Analog Supply Voltage Range
Digital Supply Voltage Range
Output Supply Voltage Range
Analog Supply Current
Digital + Output Supply Current
Analog Power Dissipation
AV
CC
DV
CC
DRV
CC
I
AVCC
I
DVCC
+
DRV
CC
PDISS
f
CLK
= 65MHz, C
LOAD
= 5pF
(Note 2)
(Note 2)
5 ±3%
2.5 to 3.5
2.5 to 3.5
382
35.5
2000
447
42
V
V
V
mA
mA
mW
Duty cycle
t
AD
t
DAT
t
DAV
t
LATENCY
t
DNV
t
DGV
t
SETUP
t
HOLD
(Note 3)
(Note 3)
(Note 3)
(Note 3)
2.5
3.2
t
CLKP
+ 0.2
(Note 3)
(Note 3)
2.8
5.3
50
±5
230
4.1
6.3
3
3.4
4.4
t
CLKP
+ 1.7
5.2
7.4
t
CLKP
+ 2.8
6.5
8.6
%
ps
ns
ns
Clock
cycles
ns
ns
ns
ns
t
CLKN
- t
CLKN
- t
CLKN
-
3.5
2.7
2.0
Note 1:
Dynamic performance is based on a 32,768-point data record with a sampling frequency of f
SAMPLE
= 65.0117120MHz, an
input frequency of f
IN
= f
SAMPLE
x (35283/32768) = 70.001472MHz, and a frequency bin size of 1984Hz. Close-in (f
IN
±23.8kHz) and low-frequency (DC to 47.6kHz) bins are excluded from the spectrum analysis.
Note 2:
Apply the same voltage levels to DV
CC
and DRV
CC
Note 3:
Guaranteed by design and characterization.
4
_______________________________________________________________________________________
15-Bit, 65Msps ADC with -78.2dBFS
Noise Floor for IF Applications
MAX1418
Typical Operating Characteristics
(AV
CC
= 5V, DV
CC
= DRV
CC
= 2.5V, INP and INN driven differentially with a -2dBFS amplitude, CLKP and CLKN driven differentially
with a 2V
P-P
sinusoidal input signal, C
L
= 5pF at digital outputs, f
CLK
= 65MHz, T
A
= 25°C. All AC data based on a 32k-point FFT
record and under coherent sampling conditions.)
FFT PLOT
(32,768-POINT DATA RECORD,
COHERENT SAMPLING)
f
CLK
= 65.0117MHz
f
IN
= 15.0010MHz
A
IN
= -1.97dBFS
SNR = 75dB
SFDR1 = 87.8dBc
SFDR2 = 94.7dBc
HD2 = -96.9dBc
HD3 = -87.8dBc
MAX1418 toc01
FFT PLOT
(32,768-POINT DATA RECORD,
COHERENT SAMPLING)
MAX1418 toc02
FFT PLOT
(32,768-POINT DATA RECORD,
COHERENT SAMPLING)
f
CLK
= 65.0117MHz
f
IN
= 70.0015MHz
A
IN
= -2.02dBFS
SNR = 73.7dB
SFDR1 = 85.6dBc
SFDR2 = 91.2dBc
HD2 = -85.6dBc
HD3 = -96.9dBc
MAX1418 toc03
MAX1418toc06
0
-20
AMPLITUDE (dBFS)
-40
-60
-80
-100
-120
0
5
10
15
20
25
30
ANALOG INPUT FREQUENCY (MHz)
0
-20
AMPLITUDE (dBFS)
-40
-60
-80
-100
-120
0
5
10
15
20
25
30
ANALOG INPUT FREQUENCY (MHz)
f
CLK
= 65.0117MHz
f
IN
= 34.9997MHz
A
IN
= -1.98dBFS
SNR = 74.8dB
SFDR1 = 86.55dBc
SFDR2 = 93.5dBc
HD2 = -92.6dBc
HD3 = -86.4dBc
0
-20
AMPLITUDE (dBFS)
-40
-60
-80
-100
-120
0
5
10
15
20
25
30
ANALOG INPUT FREQUENCY (MHz)
FFT PLOT
(32,768-POINT DATA RECORD,
COHERENT SAMPLING)
f
CLK
= 65.0117MHz
f
IN
= 169.9992MHz
A
IN
= -6.01dBFS
SNR = 68.5dBc
SFDR1 = 67.5dBc
SFDR2 = 82.1dBc
HD2 = -67.5dBc
HD3 = -73.6dBc
MAX1418 toc04
SNR vs. ANALOG INPUT FREQUENCY
(f
CLK
= 65.0117MHz, A
IN
= -2dBFS)
76
75
74
SNR (dB)
73
72
71
70
SFDR1/SFDR2 (dBc)
MAX1418toc05
SFDR1/SFDR2 vs. ANALOG INPUT FREQUENCY
(f
CLK
= 65.0117MHz, A
IN
= -2dBFS)
105
0
-20
AMPLITUDE (dBFS)
-40
-60
-80
-100
-120
0
5
10
15
20
25
30
ANALOG INPUT FREQUENCY (MHz)
77
95
SFDR2
85
75
SFDR1
65
69
68
5
25
45
65
85 105 125 145 165 185
f
IN
(MHz)
55
5
25
45
65
85 105 125 145 165 185
f
IN
(MHz)
_______________________________________________________________________________________
5
工作这点儿事
京公网安备 11010802033920号
Copyright © 2005-2026 EEWORLD.com.cn, Inc. All rights reserved
电子工程世界
