19-1365; Rev 0; 5/98
Low-Cost, 1%-Accurate Signal Conditioner
for Piezoresistive Sensors
General Description
The MAX1450 sensor signal conditioner is optimized for
piezoresistive sensor calibration and temperature com-
pensation. It includes an adjustable current source for
sensor excitation and a 3-bit programmable-gain amplifi-
er (PGA). Achieving a total typical error factor within
1% of the sensor’s inherent repeatability errors, the
MAX1450 compensates offset, full-span output (FSO), off-
set tempco, FSO tempco, and FSO nonlinearity of silicon
piezoresistive sensors via external trimmable resistors,
potentiometers, or digital-to-analog converters (DACs).
The MAX1450 is capable of compensating sensors that
display close error distributions with a single tempera-
ture point, making it ideal for low-cost, medium-accuracy
applications. Although optimized for use with popular
piezoresistive sensors, it may also be used with other
resistive sensor types such as strain gauges.
o
1% Sensor Signal Conditioning
o
Corrects Sensor Errors Using Coefficients Stored
in External Trimmable Resistors, Potentiometers,
or DACs
o
Compensates Offset, Offset TC, FSO, FSO TC,
and FSO Linearity
o
Rail-to-Rail
®
Analog Output
o
Programmable Current Source for Sensor
Excitation
o
Fast Signal-Path Settling Time (< 1ms)
o
Accepts Sensor Outputs from 10mV/V to 30mV/V
o
Fully Analog Signal Path
Features
MAX1450
Customization
Maxim can customize the MAX1450 for unique require-
ments including improved power specifications. With a
dedicated cell library consisting of more than 90 sen-
sor-specific functional blocks, Maxim can quickly pro-
vide customized MAX1450 solutions. Contact the
factory for additional information.
PART
MAX1450CAP
MAX1450C/D
MAX1450EAP
Ordering Information
TEMP. RANGE
0°C to +70°C
0°C to +70°C
-40°C to +85°C
PIN-PACKAGE
20 SSOP
Dice*
20 SSOP
Applications
Piezoresistive Pressure and Acceleration
Transducers and Transmitters
Manifold Absolute Pressure (MAP) Sensors
Automotive Systems
Hydraulic Systems
Industrial Pressure Sensors
*
Dice are tested at T
A
= +25°C, DC parameters only.
Rail-to-Rail is a registered trademark of Nippon Motorola, Ltd.
Functional Diagram
FSOTRIM V
DD
Pin Configuration
TOP VIEW
INP 1
I.C. 2
I.C. 3
SOTC 4
SOFF 5
A1 6
A0 7
OFFTC 8
OFFSET 9
BBUF 10
20 INM
19 V
SS
18 BDRIVE
17 ISRC
ISRC
CURRENT
SOURCE
V
DD
MAX1450
A2
A1
A0
BDRIVE
INP
INM
+
PGA
-
SOTC
SOFF
OFFTC
OFFSET
A=1
BBUF
OUT
MAX1450
16 I.C.
15 V
DD
14 OUT
13 A2
12 I.C.
11 FSOTRIM
SSOP
V
SS
________________________________________________________________
Maxim Integrated Products
1
For free samples & the latest literature: http://www.maxim-ic.com, or phone 1-800-998-8800.
For small orders, phone 408-737-7600 ext. 3468.
Low-Cost, 1%-Accurate Signal Conditioner
for Piezoresistive Sensors
MAX1450
ABSOLUTE MAXIMUM RATINGS
Supply Voltage, V
DD
to V
SS
......................................-0.3V to +6V
All Other Pins ...................................(V
SS
- 0.3V) to (V
DD
+ 0.3V)
Short-Circuit Duration, OUT, BBUF, BDRIVE .............Continuous
Continuous Power Dissipation (T
A
= +70°C)
SSOP (derate 8.00mW/°C above +70°C) ....................640mW
Operating Temperature Range
MAX1450CAP .....................................................0°C to +70°C
MAX1450EAP ..................................................-40°C to +85°C
Storage Temperature Range .............................-65°C to +165°C
Lead Temperature (soldering, 10sec) .............................+300°C
Stresses beyond those listed under “Absolute Maximum Ratings” may cause permanent damage to the device. These are stress ratings only, and functional
operation of the device at these or any other conditions beyond those indicated in the operational sections of the specifications is not implied. Exposure to
absolute maximum rating conditions for extended periods may affect device reliability.
ELECTRICAL CHARACTERISTICS
(V
DD
= +5V, V
SS
= 0, T
A
= T
MIN
to T
MAX
, unless otherwise noted. Typical values are at T
A
= +25°C.)
PARAMETER
GENERAL CHARACTERISTICS
Supply Voltage
Supply Current
ANALOG INPUT (PGA)
Input Impedance
Input-Referred Offset
Temperature Coefficient
Amplifier Gain Nonlinearity
Output Step-Response Time
Common-Mode Rejection Ratio
Input-Referred Adjustable Offset
Range
Input-Referred Adjustable
Full-Span Output Range
SUMMING JUNCTION (Figure 1)
Offset Gain
∆
V
OUT
∆
V
OFFSET
∆
V
OUT
∆
V
OFFTC
SYMBOL
V
DD
I
DD
R
IN
(Notes 2, 3)
CONDITIONS
MIN
4.5
TYP
5.0
2.8
1.0
±0.5
0.01
MAX
5.5
3.5
UNITS
V
mA
MΩ
µV/°C
%V
DD
ms
dB
mV
mV/V
T
A
= +25°C (Note 1)
63% of final value
CMRR
From V
SS
to V
DD
(Note 4)
(Note 5)
1
90
±100
10 to 30
1.15
V/V
Offset TC Gain
ANALOG OUTPUT (PGA)
Differential Signal Range Gain
Minimum Differential Signal
Gain
Differential Signal Path
Temperature Coefficient
1.15
V/V
Eight selectable gains (Table 3)
36
At any gain
5kΩ load to V
SS
or V
DD,
T
A
= +25°C
V
SS +
0.25
V
SS +
0.05
-1.0
(sink)
39 to 221
39
±50
V
DD -
0.25
44
V/V
V/V
ppm/°C
Output Voltage Swing
No load, T
A
= T
MIN
to T
MAX
Output Current Range
Output Noise
V
OUT
= (V
SS
+ 0.25V) to (V
DD
- 0.25V)
,
T
A
= +25°C
DC to 10Hz, gain = 39,
sensor impedance = 5kΩ
V
DD -
0.05
1.0
(source)
500
V
mA
µV
RMS
2
_______________________________________________________________________________________
Low-Cost, 1%-Accurate Signal Conditioner
for Piezoresistive Sensors
ELECTRICAL CHARACTERISTICS (continued)
(V
DD
= +5V, V
SS
= 0, T
A
= T
MIN
to T
MAX
, unless otherwise noted. Typical values are at T
A
= +25°C.)
PARAMETER
CURRENT SOURCE
Bridge Current Range
Bridge Voltage Swing
Current-Source Gain
Current-Source Input Voltage
Range
BUFFER (BBUF)
Voltage Swing
Current Drive
Offset Voltage
Note 1:
Note 2:
Note 3:
Note 4:
Note 5:
V
OFS
No load
V
BDRIVE
= 2.5V
(V
BDRIVE
- V
BBUF
) at V
BDRIVE
= 2.5V, no load
V
SS +
1.3
-100
-20
V
DD -
1.3
100
20
V
µA
mV
I
BDRIVE
V
BDRIVE
AA
V
ISRC
∆
BDRIVE/
∆
ISRC
(Figure 2)
I
I
V
SS +
1.3
0.1
V
SS +
1.3
13
V
DD-
1.3
0.5
2.0
V
DD -
1.3
mA
V
µA/µA
V
SYMBOL
CONDITIONS
MIN
TYP
MAX
UNITS
MAX1450
3
Contact factory for high-volume applications requiring less than 1.5mA.
All electronics temperature errors are compensated together with the sensor errors.
The sensor and the MAX1450 must always be at the same temperature during calibration and use.
This is the maximum allowable sensor offset at minimum gain (39V/V).
This is the sensor’s sensitivity normalized to its drive voltage, assuming a desired full-span output (FSO) of 4V and a bridge
voltage of 2.5V. Operating at lower bridge excitation voltages can accommodate higher sensitivities.
_______________________________________________________________________________________
Low-Cost, 1%-Accurate Signal Conditioner
for Piezoresistive Sensors
MAX1450
Pin Description
PIN
1
2, 3,
12, 16
4
NAME
INP
I.C.
FUNCTION
Positive Sensor Input. Input impedance is typically 1MΩ. Rail-to-rail input range.
Internally connected. Leave unconnected.
Offset TC Sign Bit Input. A logic low inverts V
OFFTC
with respect to V
SS.
This pin is internally pulled to V
SS
via a 1MΩ (typical) resistor. Connect to V
DD
to add V
OFFTC
to the PGA output, or leave unconnected (or
connect to V
SS
) to subtract V
OFFTC
from the PGA output.
Offset Sign Bit Input. A logic low inverts V
OFFSET
with respect to V
SS
. This pin is internally pulled to V
SS
via
a 1MΩ (typical) resistor. Connect to V
DD
to add V
OFFSET
to the PGA output, or leave unconnected (or con-
nect to V
SS
) to subtract V
OFFSET
from the PGA output.
PGA Gain-Set Input. Internally pulled to V
SS
via a 1MΩ (typical) resistor. Connect to V
DD
for a logic high or
V
SS
for a logic low.
PGA Gain-Set LSB Input. Internally pulled to V
SS
via a 1MΩ (typical) resistor. Connect to V
DD
for a logic
high or V
SS
for a logic low.
Offset TC Adjust. Analog input summed with PGA output and V
OFFSET
. Input impedance is typically 1MΩ.
Rail-to-rail input range.
Offset Adjust Input. Analog input summed with PGA output and V
OFFTC
. Input impedance is typically
1MΩ. Rail-to-rail input range.
Buffered Bridge-Voltage Output (the voltage at BDRIVE). Use with correction resistor R
STC
to correct for FSO
tempco.
Bridge Drive Current-Set Input. The voltage on this pin sets the nominal I
ISRC
. See the
Bridge Drive
section.
PGA Gain-Set MSB Input. Internally pulled to V
SS
via a 11kΩ (typical) resistor. Connect to V
DD
for a logic
high or V
SS
for a logic low.
PGA Output Voltage. Connect a 0.1µF capacitor from OUT to V
SS
.
Positive Supply Voltage Input. Connect a 0.1µF capacitor from V
DD
to V
SS
.
Current-Source Reference. Connect a 50kΩ (typical) resistor from ISRC to V
SS
.
Sensor Excitation Current Output. This pin drives a nominal 0.5mA through the bridge.
Negative Power-Supply Input.
Negative Sensor Input. Input impedance is typically 1MΩ. Rail-to-rail input range.
SOTC
5
SOFF
6
7
8
9
10
11
13
14
15
17
18
19
20
A1
A0
OFFTC
OFFSET
BBUF
FSOTRIM
A2
OUT
V
DD
ISRC
BDRIVE
V
SS
INM
______________ Detailed Description
Analog Signal Path
The MAX1450’s signal path is fully differential and com-
bines the following three stages: a 3-bit PGA with
selectable gains of 39, 65, 91, 117, 143, 169, 195, and
221; a summing junction; and a differential to single-
ended output buffer (Figure 1).
INP
PGA
INM
±
OFFSET SOFF
A2 A1 A0
OFFTC SOTC
±
Σ
A=1
OUT
Programmable-Gain Amplifier
The analog signal is first fed into a programmable-gain
instrumentation amplifier with a CMRR of 90dB and a
common-mode input range from V
SS
to V
DD
. Pins A0,
A1, and A2 set the PGA gain anywhere from 39V/V to
221V/V (in steps of 26).
4
Figure 1. Signal-Path Functional Diagram
_______________________________________________________________________________________
Low-Cost, 1%-Accurate Signal Conditioner
for Piezoresistive Sensors
Summing Junction
The second stage in the analog signal path consists of
a summing junction for offset, offset temperature com-
pensation, and the PGA output. The offset voltage
(V
OFFSET
) and offset temperature-compensation volt-
age (V
OFFTC
) add or subtract from the PGA output
depending on their respective sign bits, offset sign
(SOFF), and offset TC sign (SOTC). V
OFFSET
and
V
OFFTC
can range in magnitude from V
SS
to V
DD
.
Output Buffer
The final stage in the analog signal path consists
of a unity-gain buffer. This buffer is capable of swinging
to within 250mV of V
SS
and V
DD
while sourcing/sinking
up to 1.0mA, or within 50mV of the power supplies with
no load.
Applications Information
Compensation Procedure
The following compensation procedure assumes a pres-
sure transducer with a +5V supply and an output voltage
that is ratiometric to the supply voltage (see
Ratiometric
Output Configuration
section). The desired offset voltage
(V
OUT
at P
MIN
) is 0.5V, and the desired FSO voltage
(V
OUT
(P
MAX
) - V
OUT
(P
MIN
)) is 4V; thus the FS output volt-
age (V
OUT
at P
MAX
) will be 4.5V. The procedure requires
a minimum of two test pressures (e.g., zero and full scale)
and two temperatures. A typical compensation procedure
is as follows:
1) Perform Coefficient Initialization
2) Perform FSO Calibration
3) Perform FSO TC Compensation
4) Perform OFFSET TC Compensation
5) Perform OFFSET Calibration
6) Perform Linearity Calibration (Optional)
MAX1450
Bridge Drive
Figure 2 shows the functional diagram of the on-chip
current source. The voltage at FSOTRIM, in conjunction
with R
ISRC
, sets the nominal current, I
ISRC
which sets
the FSO (refer to Figure 3 for sensor terminology.) I
ISRC
is additionally modulated by components from the
external resistor R
STC
and the optional resistor R
LIN
.
R
STC
is used to feed back a portion of the buffered
bridge-excitation voltage (V
BBUF
), which compensates
FSO TC errors by modulating the bridge-excitation cur-
rent over temperature. To correct FSO linearity errors,
feed back a portion of the output voltage to the current-
source reference node via the optional R
LIN
resistor.
Coefficient Initialization
Select the resistor values and the PGA gain to prevent
gross overload of the PGA and bridge current source.
These values depend on sensor behavior and require
some sensor characterization data. This data may be
available from the sensor manufacturer. If not, it can be
generated by performing a two-temperature, two-pres-
V
DD
FSOTRIM
MAX1450
I
BDRIVE
≈
13 (I
ISRC
)
V
BDRIVE
A=1
BBUF
I
ISRC
R
STC
(EXTERNAL)
BBUF
OUT
R
LIN
(OPTIONAL)
(EXTERNAL)
I
ISRC
BDRIVE
INP
INM
R
ISRC
(EXTERNAL)
SENSOR
Figure 2. Bridge Drive Circuit
_______________________________________________________________________________________
5
FPGA/CPLD
京公网安备 11010802033920号
Copyright © 2005-2026 EEWORLD.com.cn, Inc. All rights reserved
电子工程世界
