FEMTOCLOCKS™ CRYSTAL-TO-3.3V
LVPECL FREQUENCY SYNTHESIZER
ICS843S050DI-02
G
ENERAL
D
ESCRIPTION
The ICS843S050DI-02 is a 10 output 3.3V LVPECL
Synthesizer optimized to generate micro-processor
HiPerClockS™
reference clock frequencies and is a member of the
HiPerClocks
TM
family of high performance clock
solutions from IDT. Using a 25MHz parallel resonant
crystal, the following frequencies can be generated on QAx or
QBx output pins: 100MHz, 133.33MHz, 166.66MHz, 175MHz,
187.5MHz, or 200MHz. The ICS843S050DI-02 is packaged in a
48-pin TQFP package.
F
EATURES
• Ten differential 3.3V LVPECL outputs and
one differential reference output
• Selectable crystal oscillator interface or
differential LVPECL input
• Supports the following output frequencies: 100MHz,
133.33MHz, 166.66MHz, 175MHz, 187.5MHz, or 200MHz
• Spread spectrum for EMI reduction
• Serial 3 wire programming interface
• VCO range: 1750MHz - 2000MHz
• RMS phase jitter @ 133.33MHz, using a 25MHz crystal
(12kHz – 30MHz): 1.38ps (typical)
• Full 3.3V supply mode
• -40°C to 85°C ambient operating temperature
• Available in both standard (RoHS 5) and lead-free (RoHS 6)
packages
IC
S
P
IN
A
SSIGNMENT
48 47 46 45 44 43 42 41 40 39 38 37
REF_OUT
nREF_OUT
V
CC
REF_CLK
nREF_CLK
XTAL_SEL
XTAL_IN
XTAL_OUT
nPLL_SEL
MR
V
CCA
V
CC
1
2
3
4
5
48-Pin TQFP, E-Pad
6
7mm x 7mm x 1mm
7
package body
8
Y Package
9
Top View
10
11
12
13 14 15 16 17 18 19 20 21 22 23 24
36
35
34
33
32
31
30
29
28
27
26
25
nQA5
QA5
nQA4
QA4
nQA3
QA3
nQA2
QA2
nQA1
QA1
nQA0
QA0
V
CC
V
EE
QB0
nQB0
QB1
nQB1
QB2
nQB2
QB3
nQB3
V
EE
V
CC
F
REQUENCY
S
ELECT
F
UNCTION
T
ABLE
Inputs
Input
Freq.
(MHz)
25MHz
25MHz
25MHz
25MHz
25MHz
25MHz
NA/NB
[1:0]
11
10
01
00
00
00
FB_DIV
[1:0]
00
00
00
11
10
00
VCO
(MHz)
2000
2000
2000
1750
1875
2000
FB
Div.
Value
80
80
80
70
75
80
N
Div.
Value
20
15
12
10
10
10
Output
Freq.
(MHz)
100
133.33
166.66
175
187.5
200
ICS843S050DI-02
FB_DIV0
FB_DIV1
NB0
NB1
NA0
NA1
S_LOAD
S_DATA
S_CLOCK
nP_LOAD
V
EE
V
CC
B
LOCK
D
IAGRAM
nPLL_SEL
Pulldown
NA
÷10
÷12
÷15
÷20
6
QA0:QA5
nQA0:nQA5
1
XTAL_IN
OSC
XTAL_OUT
REF_CLK
Pulldown
nREF_CLK
Pullup/Pulldown
nXTAL_SEL
Pulldown
0
Phase
Detector
VCO
0
1
FB_DIV
M =
÷
70,
÷
75,
÷
80
NB
÷10
÷12
÷15
÷20
4
QB0:QB3
nQB0:nQB3
REF_OUT
MR
Pulldown
NA[1:0], NB[1:0], FB_DIV[1:0]
S_LOAD
S_DATA
S_CLOCK
nP_LOAD
Pullup
Pulldown
Pulldown
Pulldown
Pullup
nREF_OUT
6
Configuration Interface Logic
IDT
™
/ ICS
™
3.3V LVPECL FREQUENCY SYNTHESIZER
1
ICS843S050DYI-02 REV. A MARCH 14, 2008
ICS843S050DI-02
FEMTOCLOCKS™ CRYSTAL-TO-3.3V LVPECL FREQUENCY SYNTHESIZER
T
ABLE
1. P
IN
D
ESCRIPTIONS
Number
1,
2
3, 12, 24,
37, 48
4
5
6
7,
8
9
Name
REF_OUT,
nREF_OUT
V
CC
REF_CLK
nREF_CLK
nXTAL_SEL
XTAL_IN,
XTAL_OUT
nPLL_SEL
Type
Output
Power
Input
Input
Input
Input
Input
Description
25MHz reference output pair. LVPECL interface levels.
Core supply pins.
Pulldown Non-inver ting differential LVPECL reference clock.
Pullup/ Inver ting differential LVPECL reference clock. V
CC
/2 default when left
Pulldown floating.
Selects between cr ystal or REF_CLK inputs as the the PLL reference
Pulldown source. Selects XTAL inputs when LOW. Selects REF_CLK when HIGH.
LVCMOS/LVTTL interface levels.
Parallel resonant cr ystal interface. XTAL_OUT is the output,
XTAL_IN is the input.
Selects between the PLL and REF_CLK as input to the dividers. When
Pulldown LOW, selects PLL (PLL Enable). When HIGH, bypasses the PLL (PLL
Bypass). LVCMOS/LVTTL interface levels.
Active HIGH Master Reset. When logic HIGH, the internal dividers are
reset causing the true outputs QXx to go low and the inver ted outputs
Pulldown nQXx to go high. When logic LOW, the internal dividers and the outputs
are enabled. Activation of MR required after power-up for synchronization
of Bank A and Bank B outputs. LVCMOS/LVTTL interface levels.
Analog supply pin.
Pullup
Pullup
Feedback divider selections. LVCMOS/LVTTL interface levels.
10
MR
Input
11
13,
14
15,
16
17,
18
19
20
21
22
23, 38,
47
25, 26
27, 28
29, 30
31, 32
33, 34
35, 36
39, 40
41, 42
43, 44
45, 46
V
CCA
FB_DIV0,
FB_DIV1
NB0,
NB1
NA0,
NA1
S_LOAD
S_DATA
S_CLOCK
nP_LOAD
V
EE
QA0, nQA0
QA1, nQA1
QA2, nQA2
QA3, nQA3
QA4, nQA4
QA5 nQA5
QB0, nQB0
QB1, nQB1
QB2, nQB2
QB3, nQB3
Power
Input
Input
Input
Input
Input
Input
Input
Power
Output
Output
Output
Ouput
Output
Output
Output
Output
Output
Output
Output divider selections for Bank B outputs.
LVCMOS/LVTTL interface levels.
Output divider selections for Bank A outputs.
Pullup
LVCMOS/LVTTL interface levels.
Pulldown Serial load. LVCMOS/LVTTL interface levels.
Pulldown Serial data. LVCMOS/LVTTL interface levels.
Pulldown Serial clock. LVCMOS/LVTTL interface levels.
Pullup
Parallel load. LVCMOS/LVTTL interface levels.
Negative supply pins. E-Pad connected to V
EE.
Differential Bank A output pair. LVPECL interface levels.
Differential Bank A output pair. LVPECL interface levels.
Differential Bank A output pair. LVPECL interface levels.
Differential Bank A output pair. LVPECL interface levels.
Differential Bank A output pair. LVPECL interface levels.
Differential Bank A output pair. LVPECL interface levels.
Differential Band B output pair. LVPECL interface levels.
Differential Band B output pair. LVPECL interface levels.
Differential Band B output pair. LVPECL interface levels.
Differential Band B output pair. LVPECL interface levels.
NOTE:
Pullup and Pulldown
refer to internal input resistors. See Table 2, Pin Characteristics, for typical values.
IDT
™
/ ICS
™
3.3V LVPECL FREQUENCY SYNTHESIZER
2
ICS843S050DYI-02 REV. A MARCH 14, 2008
ICS843S050DI-02
FEMTOCLOCKS™ CRYSTAL-TO-3.3V LVPECL FREQUENCY SYNTHESIZER
T
ABLE
2. P
IN
C
HARACTERISTICS
Symbol
C
IN
R
PULLDOWN
R
PULLUP
Parameter
Input Capacitance
Input Pulldown Resistor
Input Pullup Resistor
Test Conditions
Minimum
Typical
4
51
51
Maximum
Units
pF
kΩ
kΩ
T
ABLE
3A. F
EEDBACK
D
IVIDER
F
UNCTION
T
ABLE
Inputs
FB_DIV[1:0]
00
01
10
11
Feedback Divider Value
÷80
÷80
÷75
÷70
T
ABLE
3B. O
UTPUT
D
IVIDER
F
UNCTION
T
ABLE
Inputs
NA[1:0], NB[1:0]
00
01
10
11
Output Divider Value
÷10
÷12
÷15
÷20
IDT
™
/ ICS
™
3.3V LVPECL FREQUENCY SYNTHESIZER
3
ICS843S050DYI-02 REV. A MARCH 14, 2008
ICS843S050DI-02
FEMTOCLOCKS™ CRYSTAL-TO-3.3V LVPECL FREQUENCY SYNTHESIZER
A
BSOLUTE
M
AXIMUM
R
ATINGS
Supply Voltage, V
CC
Inputs, V
I
Outputs, I
O
Continuous Current
Surge Current
Storage Temperature, T
STG
4.6V
-0.5V to V
CC
+ 0.5V
50mA
100mA
-65°C to 150°C
NOTE: Stresses beyond those listed under Absolute
Maximum Ratings may cause per manent damage to the
device. These ratings are stress specifications only. Functional op-
eration of product at these conditions or any conditions beyond
those listed in the
DC Characteristics
or
AC Characteristics
is not
implied. Exposure to absolute maximum rating conditions for ex-
tended periods may affect product reliability.
Package Thermal Impedance,
θ
JA
33.1°C/W (0 mps)
T
ABLE
4A. P
OWER
S
UPPLY
DC C
HARACTERISTICS
,
V
CC
= 3.3V±5%, V
EE
= 0V, T
A
= -40°C
TO
85°C
Symbol
V
CC
V
CCA
I
CCA
I
EE
Parameter
Core Supply Voltage
Analog Supply Voltage
Analog Supply Current
Power Supply Current
Test Conditions
Minimum
3.135
V
CC
– 0.20
Typical
3. 3
3. 3
Maximum
3.465
V
CC
20
300
Units
V
V
mA
mA
T
ABLE
4B. LVCMOS / LVTTL DC C
HARACTERISTICS
,
V
CC
= 3.3V±5%, V
EE
= 0V, T
A
= -40°C
TO
85°C
Symbol
V
IH
V
IL
Parameter
Input High Voltage
Input Low Voltage
nPLL_SEL, S_LOAD,
S_CLOCK, S_DATA,
Input
nXTAL_SEL, MR
High Current
NA[1:0], NB[1:0],
FB_DIV[1:0], nP_LOAD
nPLL_SEL, S_LOAD,
S_CLOCK, S_DATA,
Input
nXTAL_SEL, MR
Low Current
NA[1:0], NB[1:0],
FB_DIV[1:0], nP_LOAD
Test Conditions
Minimum Typical
2
-0.3
V
CC
= V
IN
= 3.465
V
CC
= V
IN
= 3.465
V
CC
= 3.465V, V
IN
= 0V
V
CC
= 3.465V, V
IN
= 0V
-5
-150
Maximum
V
CC
+ 0.3
0.8
150
5
Units
V
V
µA
µA
µA
µA
I
IH
I
IL
IDT
™
/ ICS
™
3.3V LVPECL FREQUENCY SYNTHESIZER
4
ICS843S050DYI-02 REV. A MARCH 14, 2008
ICS843S050DI-02
FEMTOCLOCKS™ CRYSTAL-TO-3.3V LVPECL FREQUENCY SYNTHESIZER
T
ABLE
4C. LVPECL DC C
HARACTERISTICS
,
V
CC
= 3.3V±5%, V
EE
= 0V, T
A
= -40°C
TO
85°C
Symbol
I
IH
I
IL
V
PP
V
CMR
V
OH
V
OL
Parameter
Input High Current
Input Low Current
nREF_CLK
REF_CLK
nREF_CLK
REF_CLK
Test Conditions
V
CC
= V
IN
= 3.465V
V
CC
= V
IN
= 3.465V
V
CC
= 3.465V, V
IN
= 0V
V
CC
= 3.465V, V
IN
= 0V
-150
-5
0.3
V
EE
+ 1.5
V
CC
- 1.4
V
CC
- 2.0
1
V
CC
V
CC
- 0.9
V
CC
- 1.7
1.2
Minimum
Typical
Maximum
5
150
Units
µA
µA
µA
µA
µA
V
V
V
V
Peak-to-Peak Input Voltage; NOTE 1
Common Mode Input Voltage: NOTE 1, 2
Output High Voltage; NOTE 3
Output Low Voltage; NOTE 3
V
SWING
Peak-to-Peak Output Voltage Swing
0.6
NOTE 1: V
IL
should not be less than -0.3V.
NOTE 2: Common mode voltage is defined as V
IH
.
NOTE 3: Outputs terminated with 50
Ω
to V
CC
– 2V. See "Parameter Measurement Information" section,
"Output Load Test Circuit" diagram.
T
ABLE
5. AC C
HARACTERISTICS
,
V
CC
= 3.3V±5%, V
EE
= 0V, T
A
= -40°C
TO
85°C
Symbol
Parameter
Test Conditions
NA, NB = 1:1, FB_DIV = 0:0
NA, NB = 1:0, FB_DIV = 0:0
f
OUT
Output Frequency
NA, NB = 0:1, FB_DIV = 0:0
NA, NB = 0:0, FB_DIV = 1:1
NA, NB = 0:0, FB_DIV = 1:0
NA, NB = 0:0, FB_DIV = 0:0
Minimum
Typical
10 0
133.33
166.66
175
187.5
200
100
75
75
30
100MHz, (12kHz – 30MHz)
133.33MHz, (12kHz – 30MHz)
RMS Phase Jitter (Random);
NOTE 4
166.66MHz, (12kHz – 30MHz)
175MHz, (12kHz – 30MHz)
187.5MHz, (12kHz – 30MHz)
200MHz, (12kHz – 30MHz)
t
R
/ t
F
Output Rise/Fall Time
20% to 80%
100
1.41
1.38
1.39
1.33
1.31
1.26
400
51
Maximum
Units
MHz
MHz
MHz
MHz
MHz
MHz
ps
ps
ps
ps
ps
ps
ps
ps
ps
ps
ps
%
t
sk(o)
t
sk(b)
t
jit(cc)
Output Skew; NOTE 1, 2
Bank Skew;
NOTE 2, 3
Cycle-to-Cycle Jitter
Bank A
Bank B
QA, QB
t
jit(Ø)
odc
Output Duty Cycle
QA, QB
49
NOTE 1: Defined as skew between outputs at the same supply voltages and with equal load conditions.
Measured at V
CC
/2.
NOTE 2: This parameter is defined in accordance with JEDEC Standard 65.
NOTE 3: Defined as skew within a bank of outputs at the same voltages and with equal load conditions.
NOTE 4: Please refer to the Phase Noise Plot.
IDT
™
/ ICS
™
3.3V LVPECL FREQUENCY SYNTHESIZER
5
ICS843S050DYI-02 REV. A MARCH 14, 2008
电源技术
京公网安备 11010802033920号
Copyright © 2005-2026 EEWORLD.com.cn, Inc. All rights reserved
电子工程世界
