EVALUATION KIT AVAILABLE
MAX186/MAX188
Low-Power, 8-Channel,
Serial 12-Bit ADCs
General Description
The MAX186/MAX188 are 12-bit data-acquisition sys-
tems that combine an 8-channel multiplexer, high-
bandwidth track/hold, and serial interface together with
high conversion speed and ultra-low power consump-
tion. The devices operate with a single +5V supply or
dual ±5V supplies. The analog inputs are software con-
figurable for unipolar/bipolar and single-ended/differen-
tial operation.
The 4-wire serial interface directly connects to SPI,
QSPI™ and MICROWIRE® devices without external
logic. A serial strobe output allows direct connection to
TMS320 family digital signal processors. The
MAX186/MAX188 use either the internal clock or an
external serial-interface clock to perform successive-
approximation A/D conversions. The serial interface can
operate beyond 4MHz when the internal clock is used.
The MAX186 has an internal 4.096V reference while the
MAX188 requires an external reference. Both parts have
a reference-buffer amplifier that simplifies gain trim .
The MAX186/MAX188 provide a hard-wired
SHDN
pin
and two software-selectable power-down modes.
Accessing the serial interface automatically powers up
the devices, and the quick turn-on time allows the
MAX186/MAX188 to be shut down between every con-
version. Using this technique of powering down
between conversions, supply current can be cut to
under 10µA at reduced sampling rates.
The MAX186/MAX188 are available in 20-pin PDIP and
SO packages, and in a shrink small-outline package
(SSOP), that occupies 30% less area than an 8-pin
PDIP. For applications that call for a parallel interface,
see the MAX180/MAX181 data sheet. For anti-aliasing
filters, consult the MAX274/MAX275 data sheet.
____________________________Features
o
8-Channel Single-Ended or 4-Channel
Differential Inputs
o
Single +5V or ±5V Operation
o
Low Power: 1.5mA (Operating Mode)
2µA (Power-Down Mode)
o
Internal Track/Hold, 133kHz Sampling Rate
o
Internal 4.096V Reference (MAX186)
o
SPI-/QSPI-/MICROWIRE-/TMS320-Compatible
4-Wire Serial Interface
o
Software-Configurable Unipolar or Bipolar Inputs
o
20-Pin PDIP, SO, SSOP Packages
o
Evaluation Kit Available
Ordering Information
PART
†
MAX186_CPP+
MAX186_CWP+
MAX186_CAP+
MAX186DC/D
MAX186_EPP+
MAX186_EWP+
MAX186_EAP+
TEMP RANGE
0°C to +70°C
0°C to +70°C
0°C to +70°C
0°C to +70°C
-40°C to +85°C
-40°C to +85°C
-40°C to +85°C
PIN-PACKAGE
20 PDIP
20 SO
20 SSOP
Dice*
20 PDIP
20 SO
20 SSOP
Ordering Information continued on last page.
†Parts
are offered in grades A, B, C and D (grades defined in
Electrical Characteristics). When ordering, please specify grade.
Contact factory for availability of A-grade in SSOP package.
*Dice
are specified at +25°C, DC parameters only.
+Denotes
a lead(Pb)-free/RoHS-compliant package.
____________________Pin Configuration
TOP VIEW
CH0 1
CH1 2
CH2 3
CH3 4
CH4 5
CH5 6
CH6 7
CH7 8
V
SS
9
SHDN 10
+
20 V
DD
19 SCLK
18 CS
________________________Applications
Portable Data Logging
Data-Acquisition
High-Accuracy Process Control
Automatic Testing
Robotics
Battery-Powered Instruments
Medical Instruments
QSPI is a trademark of Motorola.
MICROWIRE is a registered trademark of National
Semiconductor.
MAX186
MAX188
17 DIN
16 SSTRB
15 DOUT
14 DGND
13 AGND
12 REFADJ
11 VREF
PDIP/SO/SSOP
For pricing, delivery, and ordering information, please contact Maxim Direct at
1-888-629-4642, or visit Maxim Integrated’s website at www.maximintegrated.com.
19-0123; Rev 5; 1/12
MAX186/MAX188
Low-Power, 8-Channel,
Serial 12-Bit ADCs
ABSOLUTE MAXIMUM RATINGS
V
DD
to AGND............................................................-0.3V to +6V
V
SS
to AGND ............................................................+0.3V to -6V
V
DD
to V
SS
..............................................................-0.3V to +12V
AGND to DGND.....................................................-0.3V to +0.3V
CH0–CH7 to AGND, DGND .............(V
SS
- 0.3V) to (V
DD
+ 0.3V)
CH0–CH7 Total Input Current...........................................±20mA
VREF to AGND ...........................................-0.3V to (V
DD
+ 0.3V)
REFADJ to AGND.......................................-0.3V to (V
DD
+ 0.3V)
Digital Inputs to DGND...............................-0.3V to (V
DD
+ 0.3V)
Digital Outputs to DGND ............................-0.3V to (V
DD
+ 0.3V)
Digital Output Sink Current .................................................25mA
Continuous Power Dissipation (TA = +70°C)
PDIP (derate 11.11mW/°C above +70°C) .....................889mW
SO (derate 10.00mW/°C above +70°C) ........................800mW
SSOP (derate 8.00mW/°C above +70°C) .....................640mW
Operating Temperature Ranges
MAX186_C/MAX188_C ........................................0°C to +70°C
MAX186_E/MAX188_E......................................-40°C to +85°C
Storage Temperature Range .............................-60°C to +150°C
Lead Temperature (soldering, 10s) .................................+300°C
Soldering Temperature (reflow) .......................................+260°C
Stresses beyond those listed under “Absolute Maximum Ratings” may cause permanent damage to the device. These are stress ratings only, and functional
operation of the device at these or any other conditions beyond those indicated in the operational sections of the specifications is not implied. Exposure to
absolute maximum rating conditions for extended periods may affect device reliability.
ELECTRICAL CHARACTERISTICS
(V
DD
= 5V ±5%; V
SS
= 0V or -5V; f
CLK
= 2.0MHz, external clock (50% duty cycle); 15 clocks/conversion cycle (133ksps); MAX186—
4.7µF capacitor at VREF pin; MAX188—external reference, VREF = 4.096V applied to VREF pin; T
A
= T
MIN
to T
MAX
, unless otherwise
noted.)
PARAMETER
DC ACCURACY
(Note 1)
Resolution
MAX186A/MAX188A
MAX186B/MAX188B
Relative Accuracy (Note 2)
MAX186C
MAX188C
MAX186D/MAX188D
Differential Nonlinearity
DNL
No missing codes over temperature
MAX186A/MAX188A
Offset Error
MAX186B/MAX188B
MAX186C/MAX188C
MAX186D/MAX188D
MAX186 (all grades)
MAX188A
Gain Error (Note 3)
External reference
4.096V (MAX188)
MAX188B
MAX188C
MAX188D
Gain Temperature Coefficient
Channel-to-Channel
Offset Matching
Signal-to-Noise + Distortion Ratio
Total Harmonic Distortion
(up to the 5th harmonic)
Spurious-Free Dynamic Range
Channel-to-Channel Crosstalk
SINAD
THD
SFDR
65kHz, V
IN
= 4.096V
P-P
(Note 4)
80
-85
70
-80
External reference, 4.096V
±0.8
±0.1
12
±0.5
±0.5
±1.0
±0.75
±1.0
±1
±2.0
±3.0
±3.0
±3.0
±3.0
±1.5
±2.0
±2.0
±3.0
ppm/°C
LSB
LSB
LSB
LSB
LSB
Bits
SYMBOL
CONDITIONS
MIN
TYP
MAX
UNITS
DYNAMIC SPECIFICATIONS
(10kHz sine wave input, 4.096V
P-P
, 133ksps, 2.0MHz external clock, bipolar input mode)
dB
dB
dB
dB
2
Maxim Integrated
MAX186/MAX188
Low-Power, 8-Channel,
Serial 12-Bit ADCs
ELECTRICAL CHARACTERISTICS (continued)
(V
DD
= 5V ±5%; V
SS
= 0V or -5V; f
CLK
= 2.0MHz, external clock (50% duty cycle); 15 clocks/conversion cycle (133ksps); MAX186—
4.7µF capacitor at VREF pin; MAX188—external reference, VREF = 4.096V applied to VREF pin; T
A
= T
MIN
to T
MAX
, unless otherwise
noted.)
PARAMETER
Small-Signal Bandwidth
Full-Power Bandwidth
CONVERSION RATE
Conversion Time (Note 5)
Track/Hold Acquisition Time
Aperture Delay
Aperture Jitter
Internal Clock Frequency
External compensation, 4.7µF
External Clock Frequency Range
ANALOG INPUT
Input Voltage Range,
Single-Ended and Differential
(Note 9)
Multiplexer Leakage Current
Input Capacitance
Unipolar, V
SS
= 0V
Bipolar, V
SS
= -5V
On/off leakage current, V
IN
= ±5V
(Note 6)
4.076
±0.01
16
4.096
±30
±30
±30
2.5
0
4.7
0.01
0.01
±1.5
V
DD
+
50mV
200
12
V
DD
-
50mV
20
1.5
10
350
mV
µF
µF
%
4.116
30
MAX186A, MAX186B, MAX186_C
MAX186C
MAX186_E
MAX186D
Load Regulation (Note 7)
Capacitive Bypass at VREF
Capacitive Bypass at REFADJ
REFADJ Adjustment Range
EXTERNAL REFERENCE AT VREF
(Buffer disabled, VREF = 4.096V)
Input Voltage Range
Input Current
Input Resistance
Shutdown VREF Input Current
Buffer Disable Threshold REFADJ
2.50
V
µA
kΩ
µA
V
0 to 0.5mA output load
Internal compensation
External compensation
Internal compensation
External compensation
±50
±60
ppm/°C
0 to
VREF
±VREF/2
±1
µA
pF
V
mA
Internal compensation (Note 6)
Used for data transfer only
0.1
0.1
10
t
CONV
t
AZ
10
<50
1.7
2.0
0.4
MHz
Internal clock
External clock, 2MHz, 12 clocks/conversion
5.5
6
1.5
10
µs
µs
ns
ps
MHz
SYMBOL
-3dB rolloff
CONDITIONS
MIN
TYP
4.5
800
MAX
UNITS
MHz
kHz
V
INTERNAL REFERENCE
(MAX186 only, reference buffer enabled)
T
A
= +25°C
VREF Output Voltage
VREF Short-Circuit Current
VREF Tempco
Maxim Integrated
3
MAX186/MAX188
Low-Power, 8-Channel,
Serial 12-Bit ADCs
ELECTRICAL CHARACTERISTICS (continued)
(V
DD
= 5V ±5%; V
SS
= 0V or -5V; f
CLK
= 2.0MHz, external clock (50% duty cycle); 15 clocks/conversion cycle (133ksps); MAX186—
4.7µF capacitor at VREF pin; MAX188—external reference, VREF = 4.096V applied to VREF pin; T
A
= T
MIN
to T
MAX
, unless otherwise
noted.)
PARAMETER
SYMBOL
CONDITIONS
Internal compensation mode
External compensation mode
MAX186
MAX188
MAX186
MAX188
V
INH
V
INL
V
HYST
I
IN
C
IN
V
INH
V
INL
I
INH
I
INL
V
IM
V
FLT
V
SHDN
= open
V
SHDN
= open
-100
V
SHDN
= V
DD
V
SHDN
= 0V
-4.0
1.5
2.75
100
V
DD
-1.5
V
IN
= 0V or V
DD
(Note 6)
V
DD
- 0.5
0.5
4.0
0.15
±1
15
2.4
0.8
MIN
0
4.7
1.678
1.638
±50
±5
TYP
MAX
UNITS
EXTERNAL REFERENCE AT REFADJ
Capacitive Bypass at VREF
Reference-Buffer Gain
REFADJ Input Current
DIGITAL INPUTS (DIN, SCLK,
CS
,
SHDN
)
DIN, SCLK,
CS
Input High Voltage
DIN, SCLK,
CS
Input Low Voltage
DIN, SCLK,
CS
Input Hysteresis
DIN, SCLK,
CS
Input Leakage
DIN, SCLK,
CS
Input Capacitance
SHDN
Input High Voltage
SHDN
Input Low Voltage
SHDN
Input Current, High
SHDN
Input Current, Low
SHDN
Input Mid Voltage
SHDN
Voltage, Open
SHDN
Max Allowed Leakage,
Mid Input
DIGITAL OUTPUTS (DOUT, SSTRB)
Output Voltage Low
Output Voltage High
Three-State Leakage Current
Three-State Output Capacitance
POWER REQUIREMENTS
Positive Supply Voltage
Negative Supply Voltage
V
DD
V
SS
Operating mode
Positive Supply Current
I
DD
Fast power-down
Full power-down
Negative Supply Current
I
SS
Operating mode and fast power-down
Full power-down
5 ±5%
0 or
-5 ±5%
1.5
30
2
2.5
70
10
50
10
V
V
mA
µA
µA
V
OL
V
OH
I
L
C
OUT
I
SINK
= 5mA
I
SINK
= 16mA
I
SOURCE
= 1mA
V
CS
= 5V
V
CS
= 5V (Note 6)
4
±10
15
0.3
0.4
V
V
µA
pF
V
V
V
µA
pF
V
V
µA
µA
V
V
nA
µF
V/V
µA
4
Maxim Integrated
MAX186/MAX188
Low-Power, 8-Channel,
Serial 12-Bit ADCs
ELECTRICAL CHARACTERISTICS (continued)
(V
DD
= 5V ±5%; V
SS
= 0V or -5V; f
CLK
= 2.0MHz, external clock (50% duty cycle); 15 clocks/conversion cycle (133ksps); MAX186—
4.7µF capacitor at VREF pin; MAX188—external reference, VREF = 4.096V applied to VREF pin; T
A
= T
MIN
to T
MAX
, unless otherwise
noted.)
PARAMETER
Positive Supply Rejection
(Note 8)
Negative Supply Rejection
(Note 8)
SYMBOL
PSR
PSR
CONDITIONS
V
DD
= 5V ±5%; external reference, 4.096V;
full-scale input
V
SS
= -5V ±5%; external reference, 4.096V;
full-scale input
MIN
TYP
±0.06
±0.01
MAX
±0.5
±0.5
UNITS
mV
mV
TIMING CHARACTERISTICS
(V
DD
= 5V ±5%; V
SS
=0V or -5V, T
A
= T
MIN
to T
MAX
, unless otherwise noted.)
PARAMETER
Acquisition Time
DIN to SCLK Setup
DIN to SCLK Hold
SCLK Fall to Output Data Valid
CS
Fall to Output Enable
CS
Rise to Output Disable
CS
to SCLK Rise Setup
CS
to SCLK Rise Hold
SCLK Pulse Width High
SCLK Pulse Width Low
SCLK Fall to SSTRB
CS
Fall to SSTRB Output Enable
(Note 6)
CS
Rise to SSTRB Output Disable
(Note 6)
SSTRB Rise to SCLK Rise
(Note 6)
SYMBOL
t
AZ
t
DS
t
DH
t
DO
t
DV
t
TR
t
CSS
t
CSH
t
CH
t
CL
t
SSTRB
t
SDV
t
STR
t
SCK
C
LOAD
= 100pF
External clock mode only, C
LOAD
= 100pF
External clock mode only, C
LOAD
= 100pF
Internal clock mode only
0
C
LOAD
= 100pF
C
LOAD
= 100pF
C
LOAD
= 100pF
100
0
200
200
200
200
200
MAX18_ _C/E
20
CONDITIONS
MIN
1.5
100
0
150
100
100
TYP
MAX
UNITS
µs
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
Note 1:
Tested at V
DD
= 5.0V; V
SS
= 0V; unipolar input mode.
Note 2:
Relative accuracy is the deviation of the analog value at any code from its theoretical value after the full-scale range has
been calibrated.
Note 3:
MAX186 – internal reference, offset nulled; MAX188 – external reference (VREF = +4.096V), offset nulled.
Note 4:
Ground on-channel; sine wave applied to all off channels.
Note 5:
Conversion time defined as the number of clock cycles times the clock period; clock has 50% duty cycle.
Note 6:
Guaranteed by design. Not subject to production testing.
Note 7:
External load should not change during conversion for specified accuracy.
Note 8:
Measured at V
SUPPLY
+5% and VSUPPLY -5% only.
Note 9:
The common-mode range for the analog inputs is from V
SS
to V
DD
.
Maxim Integrated
5
FPGA/CPLD
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