• Bidirectional/differential data strobe per byte of
data (DQS/DQS#)
• Programmable READ and WRITE latencies (RL/WL)
• Programmable burst lengths: 4, 8, or 16
• Per-bank refresh for concurrent operation
• On-chip temperature sensor to control self refresh
rate
• Partial-array self refresh (PASR)
• Deep power-down mode (DPD)
• Selectable output drive strength (DS)
• Clock stop capability
• RoHS-compliant, “green” packaging
Table 1: Key Timing Parameters
Speed
Grade
-18
2
-25
-3
Clock
Rate
(MHz)
533
400
333
Data Rate
(Mb/s/pin) RL WL
1066
800
667
8
6
5
4
3
2
Options
• V
DD2
: 1.2V
• Configuration
– 16 Meg x 16 x 8 banks x 1 die
– 8 Meg x 32 x 8 banks x 1 die
– 8 Meg x 32 x 8 banks x 2 die
– 16 Meg x 16 x 8 banks x 4 die
– 8 Meg x 32 x 8 banks x 2 die
– 8 Meg x 32 x 8 banks x 3 die
– 8 Meg x 32 x 8 banks x 4 die
– 16 Meg x 16 x 8 banks x 2 die +
8 Meg x 32 x 8 banks x 1 die
• Device type
– LPDDR2-S4, 1 die in package
– LPDDR2-S4, 2 die in package
– LPDDR2-S4, 3 die in package
– LPDDR2-S4, 4 die in package
• FBGA“green” package
– 134-ball FBGA (11mm x 11.5mm)
– 134-ball FBGA (11.5mm x 11.5mm)
– 168-ball FBGA (12mm x 12mm)
– 168-ball FBGA (12mm x 12mm)
– 168-ball FBGA (12mm x 12mm)
– 216-ball FBGA (12mm x 12mm)
– 216-ball FBGA (12mm x 12mm)
– 216-ball FBGA (12mm x 12mm)
– 220-ball FBGA (14mm x 14mm)
– 220-ball FBGA (14mm x 14mm)
• Timing – cycle time
– 1.875ns @ RL = 8
– 2.5ns @ RL = 6
– 3.0ns @ RL = 5
• Operating temperature range
– From –25°C to +85°C
– From –40°C to +105°C
• Revision
Notes:
Marking
L
128M16
64M32
128M32
256M32
64M64
96M64
128M64
192M32
D1
D2
D3
D4
MH
MG
KL
LE
KP
KH
KJ
KU
MP
LD
-18
2
-25
-3
IT
AT
:A
t
RCD/
t
RP
1
Typical
Typical
Typical
1. For fast
t
RCD/
t
RP, contact factory.
2. For -18 speed grade, contact factory.
PDF: 09005aef83f3f2eb
2gb_mobile_lpddr2_s4_g69a.pdf – Rev. N 3/12 EN
1
Micron Technology, Inc. reserves the right to change products or specifications without notice.
2010 Micron Technology, Inc. All rights reserved.
Products and specifications discussed herein are subject to change by Micron without notice.
2Gb: x16, x32 Mobile LPDDR2 SDRAM S4
Features
Table 2: Single Channel S4 Configuration Addressing
128 Meg x 16
Figure 3
(page 16)
CS0#
CS1#
Row addressing
Column ad-
dressing
Number of die
Die per
rank (CS#)
Ranks per
channel
1
CS0#
CS1#
CS0#
CS1#
16 Meg x 16 x 8
banks
na
16K (A[13:0])
1K (A[9:0])
na
1
1
0
1
64 Meg x 32
Figure 3
(page 16)
8 Meg x 32 x 8
banks
na
16K (A[13:0])
512 (A[8:0])
na
1
1
0
1
128 Meg x 32
Figure 4
(page 17)
8 Meg x 32 x 8
banks
8 Meg x 32 x 8
banks
16K (A[13:0])
512 (A[8:0])
512 (A[8:0])
2
1
1
2
192 Meg x 32
Figure 6
(page 19)
16 Meg x 16 x 8
banks x 2
8 Meg x 32 x 8
banks
16K (A[13:0])
1K (A[9:0])
512 (A[8:0])
3
2
1
2
256 Meg x 32
Figure 9
(page 22)
16 Meg x 16 x 8
banks x 2
16 Meg x 16 x 8
banks x 2
16K (A[13:0])
1K (A[9:0])
1K (A[9:0])
4
2
2
2
Architecture
Die configu-
ration
Table 3: Dual Channel S4 Configuration Addressing
Architecture
Die configuration
Row addressing
Column
addressing
Number of die
Die per
rank (CS#)
Ranks per
channel
1
Note:
CS0#
CS1#
Channel A
Channel B
CS0#
CS1#
64 Meg x 64
Figure 5 (page 18)
8 Meg x 32 x 8 banks
16K (A[13:0])
512 (A[8:0])
na
2
1
0
1
1
96 Meg x 64
Figure 8 (page 21)
8 Meg x 32 x 8 banks
16K (A[13:0])
512 (A[8:0])
512 (A[8:0])
3
1
1-chan A, 0-chan B
2
1
128 Meg x 64
Figure 7 (page 20)
8 Meg x 32 x 8 banks
16K (A[13:0])
512 (A[8:0])
512 (A[8:0])
4
1
1
2
2
1. A channel is a complete LPDRAM interface, including command/address and data pins.
See Package Block Diagrams (page 16) for descriptions of signal connections and die configurations for each re-
spective architecture.
PDF: 09005aef83f3f2eb
2gb_mobile_lpddr2_s4_g69a.pdf – Rev. N 3/12 EN
2
Micron Technology, Inc. reserves the right to change products or specifications without notice.
2010 Micron Technology, Inc. All rights reserved.
2Gb: x16, x32 Mobile LPDDR2 SDRAM S4
Features
Part Numbering
Figure 1: 2Gb LPDDR2 Part Numbering
MT
Micron Technology
Product Family
42 = Mobile LPDDR2 SDRAM
42
L
128M16 D1
KL
-25
IT
:A
Design Revision
:A = First generation
Operating Temperature
IT = –25°C to +85°C
AT = –40°C to +105°C
Operating Voltage
L = 1.2V
Cycle Time
Configuration
128M16 = 128 Meg x 16
64M32 = 64 Meg x 32
128M32 = 128 Meg x 32
256M32 = 256 Meg x 32
192M32 = 192 Meg x 32
64M64 = 64 Meg x 64
96M64 = 96 Meg x 64
128M64 = 128 Meg x 64
Package Codes
MH = 134-ball FBGA, 11mm x 11.5mm
MG = 134-ball FBGA, 11.5mm x 11.5mm
KL, KP, LE = 168-ball FBGA, 12mm x 12mm
KH, KJ, KU = 216-ball FBGA, 12mm x 12mm
LD, MP = 220-ball FBGA, 14mm x 14mm
-18 = 1.8ns,
t
CK RL = 8
t
-25 = 2.5ns,CK RL = 6
t
-3 = 3.0ns,CK RL = 5
Addressing
D1 = LPDDR2, 1 die
D2 = LPDDR2, 2 die
D3 = LPDDR2, 3 die
D4 = LPDDR2, 4 die
FBGA Part Marking Decoder
Due to space limitations, FBGA-packaged components have an abbreviated part marking that is different from the
part number. Micron’s FBGA part marking decoder is available at
www.micron.com/decoder.
In timing diagrams, “CMD” is used as an indicator only. Actual signals occur on CA[9:0].
V
REF
indicates V
REFCA
and V
REFDQ
.
PDF: 09005aef83f3f2eb
2gb_mobile_lpddr2_s4_g69a.pdf – Rev. N 3/12 EN
3
Micron Technology, Inc. reserves the right to change products or specifications without notice.
2010 Micron Technology, Inc. All rights reserved.
2Gb: x16, x32 Mobile LPDDR2 SDRAM S4
Features
Contents
General Description ....................................................................................................................................... 11
General Notes ............................................................................................................................................ 11
Write Data Mask ............................................................................................................................................. 67
READ Burst Followed by PRECHARGE ......................................................................................................... 69
WRITE Burst Followed by PRECHARGE ....................................................................................................... 70
Auto Precharge ........................................................................................................................................... 71
READ Burst with Auto Precharge ................................................................................................................. 71
WRITE Burst with Auto Precharge ............................................................................................................... 72
Temperature Sensor ................................................................................................................................... 87
Deep Power-Down ........................................................................................................................................ 101
Input Clock Frequency Changes and Stop Events ............................................................................................ 102
Input Clock Frequency Changes and Clock Stop with CKE LOW .................................................................. 102
Input Clock Frequency Changes and Clock Stop with CKE HIGH ................................................................. 103
NO OPERATION Command ........................................................................................................................... 103
Simplified Bus Interface State Diagram ....................................................................................................... 103
Truth Tables .................................................................................................................................................. 105
Input Signal .............................................................................................................................................. 121
AC and DC Logic Input Measurement Levels for Differential Signals ................................................................ 123
Single-Ended Requirements for Differential Signals .................................................................................... 124
Differential Input Crosspoint Voltage ......................................................................................................... 126
Clock Period Jitter .......................................................................................................................................... 138
Clock Period Jitter Effects on Core Timing Parameters ................................................................................. 138
Cycle Time Derating for Core Timing Parameters ........................................................................................ 139
Clock Cycle Derating for Core Timing Parameters ....................................................................................... 139
Clock Jitter Effects on Command/Address Timing Parameters ..................................................................... 139
Clock Jitter Effects on READ Timing Parameters .......................................................................................... 139
Clock Jitter Effects on WRITE Timing Parameters ........................................................................................ 140
AC Timing ..................................................................................................................................................... 142
CA and CS# Setup, Hold, and Derating ........................................................................................................... 149
Data Setup, Hold, and Slew Rate Derating ....................................................................................................... 156
Revision History ............................................................................................................................................ 163
Rev. N, Production – 3/12 ........................................................................................................................... 163
Rev. M, Production – 10/11 ........................................................................................................................ 163
Rev. L, Production – 09/11 .......................................................................................................................... 163
Rev. K, Production – 08/11 ......................................................................................................................... 163
Rev. J, Production – 05/11 .......................................................................................................................... 163
Rev. H, Production – 3/11 ........................................................................................................................... 163
Rev. G, Production – 1/11 ........................................................................................................................... 163
EtherCAT（Ethernet for Control Automation Technology）是一种基于以太网的开发构架的实时工业现场总线通讯协议，EtherCAT是最快的工业以太网技术之一，同时它提供纳秒级精确同步。相对于设置了相同循环时间的其他总线系统，EtherCAT系统结构通常能减少25%-30%的CPU负载，EtherCAT的出现为系统的实时性能和拓扑的灵活性树立了新的标准。...[详细]
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