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BUK9618-55A
N-channel TrenchMOS logic level FET
Rev. 02 — 16 February 2011
Product data sheet
1. Product profile
1.1 General description
Logic level N-channel enhancement mode Field-Effect Transistor (FET) in a plastic
package using TrenchMOS technology. This product has been designed and qualified to
the appropriate AEC standard for use in automotive critical applications.
1.2 Features and benefits
AEC Q101 compliant
Low conduction losses due to low
on-state resistance
Suitable for logic level gate drive
sources
Suitable for thermally demanding
environments due to 175 °C rating
1.3 Applications
12 V and 24 V loads
Automotive and general purpose
power switching
Motors, lamps and solenoids
1.4 Quick reference data
Table 1.
Symbol
V
DS
I
D
P
tot
Quick reference data
Parameter
drain-source
voltage
drain current
total power
dissipation
drain-source
on-state
resistance
Conditions
T
j
≥
25 °C; T
j
≤
175 °C
V
GS
= 5 V; T
mb
= 25 °C;
see
Figure 1;
see
Figure 3
T
mb
= 25 °C; see
Figure 2
Min
-
-
-
Typ
-
-
-
Max Unit
55
61
136
V
A
W
Static characteristics
R
DSon
V
GS
= 10 V; I
D
= 25 A;
T
j
= 25 °C
V
GS
= 4.5 V; I
D
= 25 A;
T
j
= 25 °C
V
GS
= 5 V; I
D
= 25 A;
T
j
= 25 °C; see
Figure 11;
see
Figure 12
-
-
-
12
-
14
16
19
18
mΩ
mΩ
mΩ
NXP Semiconductors
BUK9618-55A
N-channel TrenchMOS logic level FET
Quick reference data
…continued
Parameter
Conditions
Min
-
Typ
-
Max Unit
127
mJ
Table 1.
Symbol
E
DS(AL)S
Avalanche ruggedness
non-repetitive
I
D
= 61 A; V
sup
≤
55 V;
drain-source
R
GS
= 50
Ω;
V
GS
= 5 V;
avalanche energy T
j(init)
= 25 °C; unclamped
gate-drain charge V
GS
= 5 V; I
D
= 25 A;
V
DS
= 44 V; T
j
= 25 °C;
see
Figure 13
Dynamic characteristics
Q
GD
-
14
-
nC
2. Pinning information
Table 2.
Pin
1
2
3
mb
Pinning information
Symbol Description
G
D
S
D
gate
drain
source
mounting base; connected to
drain
2
1
3
mb
D
Simplified outline
Graphic symbol
G
mbb076
S
SOT404 (D2PAK)
3. Ordering information
Table 3.
Ordering information
Package
Name
BUK9618-55A
D2PAK
Description
Version
plastic single-ended surface-mounted package (D2PAK); 3 leads SOT404
(one lead cropped)
Type number
BUK9618-55A
All information provided in this document is subject to legal disclaimers.
© NXP B.V. 2011. All rights reserved.
Product data sheet
Rev. 02 — 16 February 2011
2 of 13
NXP Semiconductors
BUK9618-55A
N-channel TrenchMOS logic level FET
4. Limiting values
Table 4.
Symbol
V
DS
V
DGR
V
GS
I
D
Limiting values
Parameter
drain-source voltage
drain-gate voltage
gate-source voltage
drain current
T
mb
= 25 °C; V
GS
= 5 V; see
Figure 1;
see
Figure 3
T
mb
= 100 °C; V
GS
= 5 V; see
Figure 1
I
DM
P
tot
T
stg
T
j
I
S
I
SM
E
DS(AL)S
peak drain current
total power dissipation
storage temperature
junction temperature
source current
peak source current
non-repetitive drain-source
avalanche energy
T
mb
= 25 °C
pulsed; t
p
≤
10 µs; T
mb
= 25 °C
I
D
= 61 A; V
sup
≤
55 V; R
GS
= 50
Ω;
V
GS
= 5 V; T
j(init)
= 25 °C; unclamped
T
mb
= 25 °C; pulsed; t
p
≤
10 µs;
see
Figure 3
T
mb
= 25 °C; see
Figure 2
Conditions
T
j
≥
25 °C; T
j
≤
175 °C
R
GS
= 20 kΩ
Min
-
-
-15
-
-
-
-
-55
-55
-
-
-
Max
55
55
15
61
43
246
136
175
175
61
246
127
Unit
V
V
V
A
A
A
W
°C
°C
A
A
mJ
In accordance with the Absolute Maximum Rating System (IEC 60134).
Source-drain diode
Avalanche ruggedness
80
I
D
(A)
60
03nf37
120
P
der
(%)
80
03na19
40
40
20
0
25
50
75
100
125
150
175
200
T
mb
(°C)
0
0
50
100
150
T
mb
(°C)
200
Fig 1.
Normalized continuous drain current as a
function of mounting base temperature
Fig 2.
Normalized total power dissipation as a
function of mounting base temperature
BUK9618-55A
All information provided in this document is subject to legal disclaimers.
© NXP B.V. 2011. All rights reserved.
Product data sheet
Rev. 02 — 16 February 2011
3 of 13
NXP Semiconductors
BUK9618-55A
N-channel TrenchMOS logic level FET
10
3
I
D
(A)
10
2
03ne48
R
DSon
= V
DS
/I
D
tp = 10
μs
100
μs
10
DC
1 ms
10 ms
100 ms
1
1
10
V
DS
(V)
10
2
Fig 3.
Safe operating area; continuous and peak drain currents as a function of drain-source voltage
5. Thermal characteristics
Table 5.
Symbol
R
th(j-mb)
R
th(j-a)
Thermal characteristics
Parameter
thermal resistance from
junction to mounting base
thermal resistance from
junction to ambient
Conditions
see
Figure 4
minimum footprint; mounted on a
printed-circuit board
Min
-
-
Typ
-
50
Max
1.1
-
Unit
K/W
K/W
10
Z
th(j-mb)
(K/W)
1
δ
= 0.5
0.2
10
−1
0.1
0.05
0.02
10
−2
03ne49
P
δ
=
t
p
T
Single Shot
t
p
t
T
10
−3
10
−6
10
−5
10
−4
10
−3
10
−2
10
−1
t
p
(s)
1
Fig 4.
Transient thermal impedance from junction to mounting base as a function of pulse duration
BUK9618-55A
All information provided in this document is subject to legal disclaimers.
© NXP B.V. 2011. All rights reserved.
Product data sheet
Rev. 02 — 16 February 2011
4 of 13
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