54F 74F413 64 x 4 First-In First-Out Buffer Memory with Parallel I O
January 1995
54F 74F413
64 x 4 First-In First-Out Buffer Memory with Parallel I O
General Description
The ’F413 is an expandable fall-through type high-speed
First-In First-Out (FIFO) buffer memory organized as 64
words by four bits The 4-bit input and output registers rec-
ord and transmit respectively asynchronous data in parallel
form Control pins on the input and output allow for hand-
shaking and expansion The 4-bit wide 62-bit deep fall-
through stack has self-contained control logic
Features
Y
Y
Y
Y
Y
Y
Separate input and output clocks
Parallel input and output
Expandable without external logic
15 MHz data rate
Supply current 160 mA max
Available in SOIC (300 mil only)
Commercial
74F413PC
Military
Package
Number
N16E
Package Description
16-Lead (0 300 Wide) Molded Dual-In-Line
16-Lead Ceramic Dual-In-Line
54F413DM (Note 1)
J16A
Note 1
Military grade device with environmental and burn-in processing Use suffix
e
DMQB
Logic Symbol
Connection Diagram
Pin Assignment
for DIP
TL F 9541 – 1
TL F 9541 – 2
TRI-STATE is a registered trademark of National Semiconductor Corporation
C
1995 National Semiconductor Corporation
TL F 9541
RRD-B30M105 Printed in U S A
Unit Loading Fan Out
54F 74F
Pin Names
Description
UL
HIGH LOW
10
50
10
10
10
10
10
0 667
13 3
0 667
0 667
0 667
0 667
0 667
Input I
IH
I
IL
Output I
OH
I
OL
20
mA
b
0 4 mA
b
1 mA 8 mA
20
mA
b
0 4 mA
20
mA
b
0 4 mA
20
mA
b
0 4 mA
20
mA
b
0 4 mA
20
mA
b
0 4 mA
D
0
–D
3
O
0
–O
3
IR
SI
SO
OR
MR
Data Inputs
Data Outputs
Input Ready
Shift In
Shift Out
Output Ready
Master Reset
Functional Description
Data Input
Data is entered into the FIFO on D
0
– D
3
in-
puts To enter data the Input Ready (IR) should be HIGH
indicating that the first location is ready to accept data Data
then present at the four data inputs is entered into the first
location when the Shift In (SI) is brought HIGH An SI HIGH
signal causes the IR to go LOW Data remains at the first
location until SI is brought LOW When SI is brought LOW
and the FIFO is not full IR will go HIGH indicating that more
room is available Simultaneously data will propagate to the
second location and continue shifting until it reaches the
output stage or a full location If the memory is full IR will
remain LOW
Data Transfer
Once data is entered into the second cell
the transfer of any full cell to the adjacent (downstream)
empty cell is automatic activated by an on-chip control
Thus data will stack up at the end of the device while empty
locations will ‘‘bubble’’ to the front The t
PT
parameter de-
fines the time required for the first data to travel from input
to the output of a previously empty device
Data Output
Data is read from the O
0
–O
3
outputs When
data is shifted to the output stage Output Ready (OR) goes
HIGH indicating the presence of valid data When the OR is
HIGH data may be shifted out by bringing the Shift Out (SO)
HIGH A HIGH signal at SO causes the OR to go LOW Valid
data is maintained while the SO is HIGH When SO is
brought LOW the upstream data provided that stage has
valid data is shifted to the output stage When new valid
data is shifted to the output stage OR goes HIGH If the
FIFO is emptied OR stays LOW and O
0
–O
3
remains as
before i e data does not change if FIFO is empty
Input Ready and Output Ready
may also be used as
status signals indicating that the FIFO is completely full (In-
put Ready stays LOW for at least t
PT
) or completely empty
(Output Ready stays LOW for at least t
PT
)
Block Diagram
TL F 9541 – 4
2
Absolute Maximum Ratings
(Note 1)
If Military Aerospace specified devices are required
please contact the National Semiconductor Sales
Office Distributors for availability and specifications
Storage Temperature
Ambient Temperature under Bias
Junction Temperature under Bias
Plastic
V
CC
Pin Potential to
Ground Pin
b
65 C to
a
150 C
b
55 C to
a
125 C
b
55 C to
a
175 C
b
55 C to
a
150 C
b
0 5V to
a
7 0V
Recommended Operating
Conditions
Free Air Ambient Temperature
Military
Commercial
Supply Voltage
Military
Commercial
b
55 C to
a
125 C
0 C to
a
70 C
a
4 5V to
a
5 5V
a
4 5V to
a
5 5V
b
0 5V to
a
7 0V
Input Voltage (Note 2)
b
30 mA to
a
5 0 mA
Input Current (Note 2)
Voltage Applied to Output
in HIGH State (with V
CC
e
0V)
b
0 5V to V
CC
Standard Output
b
0 5V to
a
5 5V
TRI-STATE Output
Current Applied to Output
in LOW State (Max)
twice the rated I
OL
(mA)
Note 1
Absolute maximum ratings are values beyond which the device may
be damaged or have its useful life impaired Functional operation under
these conditions is not implied
Note 2
Either voltage limit or current limit is sufficient to protect inputs
DC Electrical Characteristics
Symbol
V
IH
V
IL
V
CD
V
OH
Parameter
Min
Input HIGH Voltage
Input LOW Voltage
Input Clamp Diode Voltage
Output HIGH
Voltage
Output LOW
Voltage
Input HIGH
Current
54F 10% V
CC
74F 10% V
CC
74F 5% V
CC
54F 10% V
CC
74F 10% V
CC
54F
74F
24
24
27
05
05
20 0
50
100
70
250
50
4 75
3 75
b
0 4
b
20
b
130
54F 74F
Typ
Max
Units
V
08
b
1 5
V
CC
Conditions
Recognized as a HIGH Signal
Recognized as a LOW Signal
20
V
V
V
Min
Min
I
IN
e b
18 mA
I
OH
e b
1 mA
I
OH
e b
1 mA
I
OH
e b
1 mA
I
OL
e
8 mA
I
OL
e
8 mA
V
IN
e
2 7V
V
IN
e
7 0V
V
OUT
e
V
CC
I
ID
e
1 9
mA
All Other Pins Grounded
V
IOD
e
150 mV
All Other Pins Grounded
V
IN
e
0 5V
V
OUT
e
0V
V
O
e
HIGH
V
OL
I
IH
I
BVI
I
CEX
V
ID
I
OD
I
IL
I
OS
I
CCH
V
mA
mA
mA
V
mA
mA
mA
mA
Min
Max
Max
Max
00
00
Max
Max
Max
Input HIGH Current 54F
Breakdown Test
74F
Output HIGH
Leakage Current
Input Leakage
Test
Output Leakage
Circuit Current
Input LOW Current
Output Short-Circuit Current
Power Supply Current
54F
74F
74F
74F
115
160
3
AC Electrical Characteristics
74F
Symbol
Parameter
Min
f
max
f
max
t
PLH
t
PHL
t
PLH
t
PHL
t
PLH
t
PHL
t
PLH
t
PLH
Shift In Rate
Shift Out Rate
Propagation Delay
Shift In to IR
Propagation Delay
Shift Out to OR
Propagation Delay
Output Data Delay
Propagation Delay
Master Reset to IR
Propagation Delay
Master Reset to OR
10
10
15
15
15
15
15
15
15
15
44 0
31 0
52 0
31 0
46 0
34 0
27 0
30 0
T
A
e a
25 C
V
CC
e a
5 0V
C
L
e
50 pF
Typ
Max
54F
T
A
V
CC
e
Mil
C
L
e
50 pF
Min
80
80
15
15
15
15
15
15
15
15
50 0
37 0
57 0
37 0
52 0
39 0
33 0
34 0
Max
74F
T
A
V
CC
e
Com
C
L
e
50 pF
Min
10
10
15
15
15
15
15
15
15
15
48 0
35 0
55 0
35 0
50 0
37 0
31 0
32 0
Max
MHz
MHz
ns
ns
ns
ns
ns
Units
AC Operating Requirements
74F
Symbol
Parameter
T
A
e a
25 C
V
CC
e a
5 0V
Min
t
s
(H)
t
s
(L)
t
h
(H)
t
h
(L)
t
w
(H)
t
w
(L)
t
w
(H)
t
w
(L)
t
w
(H)
t
w
(L)
t
w
(L)
t
rec
t
PT
Setup Time HIGH or LOW
D
n
to SI
Hold Time HIGH or LOW
D
n
to SI
Shift In Pulse Width
HIGH or LOW
Shift Out Pulse Width
HIGH or LOW
Input Ready Pulse Width
HIGH
Output Ready Pulse Width
LOW
Master Reset Pulse Width
LOW
Recovery Time MR to SI
Data Throughput Time
10
10
10 0
10 0
50
10 0
75
10 0
75
50
10 0
32 0
09
Max
54F
T
A
V
CC
e
Mil
Min
10
10
10 0
10 0
50
10 0
85
10 0
85
50
10 0
35 0
10
Max
74F
T
A
V
CC
e
Com
Min
10
10
10 0
10 0
50
10 0
75
10 0
75
50
10 0
35 0
10
ns
ns
ns
ns
ms
Max
Units
ns
ns
4
Ordering Information
The device number is used to form part of a simplified purchasing code where the package type and temperature range are
defined as follows
74F
Temperature Range Family
74F
e
Commercial
54F
e
Military
Device Type
Package Code
P
e
Plastic DIP
D
e
Ceramic DIP
413
P
C
X
Special Variations
QB
e
Military grade device with
environmental and burn-in
processing
Temperature Range
C
e
Commercial (0 C to
a
70 C)
M
e
Military (
b
55 C to
a
125 C)
Physical Dimensions
inches (millimeters)
16-Lead Ceramic Dual-In-Line Package (D)
NS Package Number J16A
5
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