ICS673-01
PLL B
UILDING
B
LOCK
Description
The ICS673-01 is a low cost, high performance Phase
Locked Loop (PLL) designed for clock synthesis and
synchronization. Included on the chip are the phase
detector, charge pump, Voltage Controlled Oscillator
(VCO), and two output buffers. One output buffer is a
divide by two of the other. Through the use of external
reference and VCO dividers (the ICS674-01), the user
can customize the clock to lock to a wide variety of
input frequencies.
The ICS673-01 also has an output enable function that
puts both outputs into a high-impedance state. The
chip also has a power down feature which turns off the
entire device.
For applications that require low jitter or jitter
attenuation, see the MK2069. For a smaller package,
see the ICS663.
Features
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Packaged in 16 pin SOIC
Access to VCO input and feedback paths of PLL
VCO operating range up to 120 MHz (5V)
Able to lock MHz range outputs to kHz range inputs
through the use of external dividers
Output Enable tri-states outputs
Low skew output clocks
Power Down turns off chip
VCO predivide to feedback divider of 1 or 4
25 mA output drive capability at TTL levels
Advanced, low power, sub-micron CMOS process
Single supply +3.3 V or +5 V ±10% operating voltage
Industrial temperature range available
Forms a complete PLL, using the ICS674-01
For better jitter performance, please use the MK1575
NOTE: EOL for non-green parts to occur on
5/13/10 per PDN U-09-01
Block Diagram
VDD
2
CHCP VCOIN
VDD
I
cp
Clock Input
REFIN
FBIN
UP
Phase/
Frequency
Detector
CLK1
VCO
2
4
1
0
DOWN
MUX
2
CLK2
I
cp
PD
(entire chip)
CAP
3
GND
SEL
OE
(both
outputs)
External Feedback Divider
(such as the ICS674-01)
MDS 673-01 K
I n t e gra te d C i r c u i t S y s t e m s
●
1
525 Race Stre et, San Jo se, CA 9 5126
●
Revision 110409
te l (40 8) 2 95-98 00
●
w w w. i c st . c o m
ICS673-01
PLL B
UILDING
B
LOCK
Pin Assignment
F B IN
VDD
VDD
GND
GND
GND
CHGP
V C O IN
1
2
3
4
5
6
7
8
16
15
14
13
12
11
10
9
R E F IN
NC
C LK1
C LK2
PD
SEL
OE
CAP
VCO Predivide Select Table
SEL
0
1
VCO Predivide
4
1
0 = connect pin directly to ground
1 = connect pin directly to VDD
1 6 p in n a rro w (1 5 0 m il) S O IC
Pin Descriptions
Pin
Number
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
Pin
Name
FBIN
VDD
VDD
GND
GND
GND
CHGP
VCOIN
CAP
OE
SEL
PD
CLK2
CLK1
NC
REFIN
Pin
Type
Input
Power
Power
Power
Power
Power
Output
Input
Input
Input
Input
Input
Output
Output
-
Input
Pin Description
Feedback clock input. Connect the feedback clock to this pin. Falling
edge triggered.
Connect to +3.3 V or +5 V and to VDD on pin 3.
Connect to VDD on pin 2.
Connect to ground.
Connect to ground.
Connect to ground.
Charge pump output. Connect to VCOIN under normal operation.
Input to internal VCO.
Loop filter return.
Output enable. Active when high. Tri-states both outputs when low.
Select pin for VCO predivide to feedback divider per table above.
Power down. Turns off entire chip when pin is low. Outputs stop low.
Clock output 2. Low skew divide by two version of CLK1.
Clock output 1.
No connect. Nothing is connected internally to this pin.
Reference input. Connect reference clock to this pin. Falling edge is
triggered.
MDS 673-01 K
In te grated Circuit Systems
●
2
525 Ra ce Street, San Jose, CA 9512 6
●
Revision 110409
tel (4 08) 295-9 800
●
w w w. i c s t . c o m
ICS673-01
PLL B
UILDING
B
LOCK
Absolute Maximum Ratings
Stresses above the ratings listed below can cause permanent damage to the ICS673-01. These ratings,
which are standard values for ICS commercially rated parts, are stress ratings only. Functional operation of
the device at these or any other conditions above those indicated in the operational sections of the
specifications is not implied. Exposure to absolute maximum rating conditions for extended periods can
affect product reliability. Electrical parameters are guaranteed only over the recommended operating
temperature range.
Item
Supply Voltage, VDD
All Inputs and Outputs
Ambient Operating Temperature
Industrial Temperature
Storage Temperature
Soldering Temperature
7V
Rating
-0.5V to VDD+0.5V
0 to +70° C
-40 to +85° C
-65 to +150° C
260° C
Recommended Operation Conditions
Parameter
Ambient Operating Temperature
Power Supply Voltage (measured in respect to GND)
Min.
0
+3.13
Typ.
Max.
+70
+5.25
Units
°
C
V
DC Electrical Characteristics
VDD=3.3V ±5% or 5.0V ±10%,
Ambient temperature -40 to +85° C, unless stated otherwise
Parameter
Operating Voltage
Logic Input High Voltage
Logic Input Low Voltage
LF Input Voltage Range
Output High Voltage
Output Low Voltage
Output High Voltage, CMOS
level
Operating Supply Current
Short Circuit Current
Input Capacitance
Symbol
VDD
V
IH
V
IL
V
I
V
OH
V
OL
V
OH
IDD
I
OS
C
I
Conditions
REFIN, FBIN,
SEL
REFIN, FBIN,
SEL
Min.
3.13
2
Typ.
Max.
5.50
Units
V
V
0.8
0
VDD
0.4
VDD-0.4
15
±100
5
V
V
V
V
I
OH
= -25 mA
I
OL
= 25mA
I
OH
= -8 mA
VDD = 5.0 V,
No load, 40 MHz
CLK
SEL
2.4
mA
mA
pF
MDS 673-01 K
In te grated Circuit Systems
●
3
525 Ra ce Street, San Jose, CA 9512 6
●
Revision 110409
tel (4 08) 295-9 800
●
w w w. i c s t . c o m
ICS673-01
PLL B
UILDING
B
LOCK
AC Electrical Characteristics
VDD = 3.3V ±5%,
Ambient Temperature -40 to +85° C, C
LOAD
at CLK = 15 pF, unless stated otherwise
Parameter
Output Clock Frequency
(from pin CLK)
Input Clock Frequency
(into pins REFIN or FBIN)
Output Rise Time
Output Fall Time
Output Clock Duty Cycle
Jitter, Absolute peak-to-peak
VCO Gain
Charge Pump Current
Symbol
f
CLK
f
REF
t
OR
t
OF
t
DC
t
J
K
O
I
cp
Conditions
SEL = 1
SEL = 0
Min.
1
0.25
Note 1
Typ.
Max. Units
100
25
8
MHz
MHz
MHz
ns
ns
%
ps
MHz/V
µA
0.8 to 2.0V
2.0 to 0.8V
At VDD/2
40
1.2
0.75
50
250
190
2.5
2
1.5
60
VDD = 5.0V ±10%,
Ambient Temperature -40 to +85° C, C
LOAD
at CLK = 15 pF,
unless stated otherwise
Parameter
Output Clock Frequency
(from pin CLK)
Input Clock Frequency
(into pins REFIN or FBIN)
Output Rise Time
Output Fall Time
Output Clock Duty Cycle
Jitter, Absolute peak-to-peak
VCO Gain
Charge Pump Current
Symbol
f
CLK
f
REF
t
OR
t
OF
t
DC
t
J
K
O
I
cp
Conditions
SEL = 1
SEL = 0
Min.
1
0.25
Note 1
Typ.
Max. Units
120
30
8
MHz
MHz
MHz
ns
ns
%
ps
MHz/V
µA
0.8 to 2.0V
2.0 to 0.8V
At VDD/2
45
0.5
0.5
50
150
190
2.4
1
1
55
Note 1: Minimum input frequency is limited by loop filter design. 1 kHz is a practical minimum limit.
External Components
The ICS673-01 requires a minimum number of external
components for proper operation. A decoupling
capacitor of 0.01µF should be connected between VDD
and GND as close to the ICS673-01 as possible. A
series termination resistor of 33
Ω
may be used at the
clock output.
Special considerations must be made in choosing loop
components C
S
and C
P
. These can be found online at
http://www.icst.com/products/telecom/loopfiltercap.htm
Avoiding PLL Lockup
In some applications, the ICS673-01 can “lock up” at
the maximum VCO frequency. This is usually caused
by power supply glitches or a very slow power supply
ramp. This situation also occurs if the external divider
starts to fail at high input frequencies. The usual failure
mode of a divider circuit is that the output of the divider
begins to miss clock edges. The phase detector
interprets this as a too low output frequency and
MDS 673-01 K
In te grated Circuit Systems
●
4
525 Ra ce Street, San Jose, CA 9512 6
●
Revision 110409
tel (4 08) 295-9 800
●
w w w. i c s t . c o m
ICS673-01
PLL B
UILDING
B
LOCK
increases the VCO frequency. The feedback divider
begins to miss even more clock edges and the VCO
frequency is continually increased until it is running at
its maximum frequency. Whether caused by power
supply issues or by the external divider, the loop can
only recover by powering down the circuit or asserting
PD.
The simplest way to avoid this problem is to use an
external divider that always operates correctly
regardless of the VCO speed. Figures 2 and 3 show
that the VCO is capable of high speeds. By using the
internal divide-by-four and/or the CLK2 output, the
maximum VCO frequency can be divided by 2, 4, or 8
and a slower counter can be used. Using the ICS673
internal dividers in this manner does reduce the
number of frequencies that can be exactly synthesized
by forcing the total VCO divide to change in increments
of 2, 4, or 8.
If this lockup problem occurs, there are several
solutions; three of which are described below.
1. If the system has a reset or power good signal, this
should be applied to the PD pin, forcing the chip to stay
powered down until the power supply voltage has
stabilized
2. If no power good signal is available, a simple
power-on reset circuit can be attached to the PD pin, as
shown in Figure 1. When the power supply ramps up,
this circuit holds PD asserted (device powered down)
until the capacitor charges.
VDD
R
1
I CS673- 01
PD
C
3
A. Basi c Ci r cui t
VDD
R
1
D
1
I CS673-01
PD
C
3
B. Fast er Di scharge
Fi g 1 . Po we r o n Re s e t Ci r c u i t s
The circuit of Figure 1A is adequate in most cases, but
the discharge rate of capacitor C3 when VDD goes low
is limited by R1. As this discharge rate determines the
minimum reset time, the circuit of Figure 1B may be
used when a faster reset time is desired. The values of
R1 and C3 should be selected to ensure that PD stays
below 1.0 V until the power supply is stable.
3. A comparator circuit may be used to monitor the loop
filter voltage as shown in Figure 2. This circuit will dump
the charge off the loop filter by asserting PD if the VCO
begins to run too fast and the PLL can recover. A good
choice for the comparator is the National
Semiconductor LMC7211BIM5X. It is low power,
version of the small (SOT-23), low cost, and has high
input impedance.
The trigger voltage of the comparator is set by the
voltage divider formed by R2 and R3. The voltage
should be set to a value higher than the VCO input is
expected to run during normal operation. Typically, this
MDS 673-01 K
In te grated Circuit Systems
●
5
525 Ra ce Street, San Jose, CA 9512 6
●
Revision 110409
tel (4 08) 295-9 800
●
w w w. i c s t . c o m
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