19-1534; Rev 1; 10/99
+3.3V, 2.5Gbps, SDH/SONET, 4-Channel
Interconnect Mux/Demux ICs with Clock Generator
General Description
The MAX3831/MAX3832 are 4:1 multiplexers (muxes)
and 1:4 demultiplexers (demuxes) with automatic chan-
nel assignment. Operating from a single +3.3V supply,
the mux receives four parallel, 622Mbps SDH/SONET
channels. These channels are bit interleaved to gener-
ate a serial data stream of 2.488Gbps for interfacing to
an optical or an electrical driver. A 10-bit-wide elastic
buffer tolerates up to ±7.5ns skew between any parallel
data input and the reference clock. An external
155MHz reference clock is required for the on-chip PLL
to synthesize a high-frequency 2.488GHz clock for tim-
ing the outgoing data streams.
The MAX3831/MAX3832’s demux receives 2.488Gbps
serial data and the 2.488GHz clock from an external
clock/data recovery device (MAX3876), converting it to
four 622Mbps LVDS outputs. The MAX3831 provides a
622MHz LVDS clock output, and the MAX3832 pro-
vides a 155MHz LVDS clock output. An internal frame
detector looks for a 622Mbps SDH/SONET framing pat-
tern and rolls the demux to maintain proper channel
assignment at the outputs.
These devices also include an embedded pattern gen-
erator that enables a full-speed, built-in self-test (BIST).
Two different loopback modes provide system test flexi-
bility. A TTL loss-of-frame monitor is included. The
MAX3831/MAX3832 are available in 64-pin TQFP-EP
(exposed paddle) packages and are specified over the
upper commercial (0°C to +85°C) temperature range.
Features
o
+3.3V Single Supply
o
1.45W Power Dissipation (MAX3831)
o
4-Channel Mux/Demux with Fully Integrated
2.488GHz Clock Generator
o
Frame Detection Maintains Channel Assignment
o
±7.5ns Elastic Store Range
o
2.5ps RMS Serial-Data Output Random Jitter
o
8ps Serial-Data Output Deterministic Jitter
o
622Mbps LVDS Parallel Input/Output
o
2.488Gbps Serial CML Input/Output
o
On-Chip Pattern Generator Provides
High-Speed BIST
o
System Test Flexibility: System Loopback,
Line Loopback
o
Loss-of-Frame Indicator
MAX3831/MAX3832
Applications
SDH/SONET Backplanes
High-Speed Parallel Links
Intrarack/Subrack
Interconnects
ATM Switching Networks
Line Extenders
Dense Digital Cross-
Connects
Ordering Information
PART
TEMP. RANGE
0°C to +85°C
0°C to +85°C
PIN-PACKAGE
64 TQFP-EP
64 TQFP-EP
MAX3831UCB
MAX3832UCB
Pin Configuration appears at end of data sheet.
Typical Application Circuit
TTL
0.33µF
TTL
TTL
TTL
+3.3V
0.1µF
RSETES
155MHz REF
CLOCK INPUT
4
4 LVDS
CMOS
OVERHEAD
4
LVDS 4
LVDS
LVDS
RCLKI+
RCLKI-
PDI1+ TO PDI4+
PDI1- TO PDI4-
PDO1+ TO PDO4+
PDO1- TO PDO4-
PCLKO+
PCLKO-
TRIEN
TTL
GND
FIL+
FIL-
TEST
LOF
PLBEN
V
CC
SCLKI-
SCLKI+
SDI-
CML
CML
MAX3876
2.5Gbps
CDR
2.5Gbps
OPTICAL
TRANSCEIVER
MAX3831
MAX3832
SDI+
SDO+
SDO-
LBEN
RSETFR
TTL
TTL
________________________________________________________________
Maxim Integrated Products
1
For free samples & the latest literature: http://www.maxim-ic.com, or phone 1-800-998-8800.
For small orders, phone 1-800-835-8769.
+3.3V, 2.5Gbps, SDH/SONET, 4-Channel
Interconnect Mux/Demux ICs with Clock Generator
MAX3831/MAX3832
ABSOLUTE MAXIMUM RATINGS
Positive Supply Voltage (V
CC
)...............................-0.5V to +5.0V
Input Voltage (LVDS, TTL)..........................-0.5V to (V
CC
+ 0.5V)
CML Input Voltage ..........................(V
CC
- 0.8V) to (V
CC
+ 0.5V)
FIL+, FIL- Voltage.......................................-0.5V to (V
CC
+ 0.5V)
TTL Output Voltage ....................................-0.5V to (V
CC
+ 0.5V)
LVDS Output Voltage ..................................-0.5V to (V
CC
+0.5V)
CML Output Currents..........................................................22mA
Continuous Power Dissipation (T
A
= +85°C) (Note 1)
64-Pin TQFP-EP (derate 40.0mW/°C above +85°C) .........2.6W
Operating Temperature Range...............................0°C to +85°C
Storage Temperature Range .............................-60°C to +150°C
Lead Temperature (soldering, 10sec) .............................+300°C
Note 1:
Based on empirical data from the MAX3831/MAX3832 evaluation kit.
Stresses beyond those listed under “Absolute Maximum Ratings” may cause permanent damage to the device. These are stress ratings only, and functional
operation of the device at these or any other conditions beyond those indicated in the operational sections of the specifications is not implied. Exposure to
absolute maximum rating conditions for extended periods may affect device reliability.
DC ELECTRICAL CHARACTERISTICS
(V
CC
= +3.0V to +3.6V, LVDS differential load = 100Ω ±1%, CML load = 50Ω ±1% to V
CC
, all TTL inputs are open, T
A
= 0°C to
+85°C, unless otherwise noted. Typical values are at T
A
= +25°C and V
CC
= +3.3V.)
PARAMETER
Supply Current
LVDS INPUTS AND OUTPUTS
Input Voltage Range
Differential Input Threshold
Threshold Hysteresis
Input Impedance
Input Common-Mode Current
Output Voltage High
Output Voltage Low
Differential Output Voltage
Change in Magnitude of
Differential Output Voltage for
Complementary States
Output Offset Voltage
Change in Magnitude of Output
Offset Voltage for Complementary
States
Differential Output Impedance
Output Current
CML INPUTS AND OUTPUTS
Differential Output Voltage
Differential Output Impedance
Output Common-Mode Voltage
Single-Ended Input Voltage Range
Differential Input Voltage Swing
Differential Input Impedance
2
V
IS
Figure 2
V
CC
-
0.6
400
85
100
V
ODp-p
640
85
800
100
V
CC
- 0.2
V
CC
+
0.4
1200
115
1000
115
mVp-p
Ω
V
V
mVp-p
Ω
V
IN
V
IDTH
V
HYST
R
IN
I
OS
V
OH
V
OL
V
OD
∆V
OD
V
OS
∆V
OS
TRIEN
= GND
TRIEN
= V
CC
Short outputs together (Note 3)
80
>1
120
12
1.125
Figure 1
0.925
250
400
±25
1.275
±25
LVDS input, V
OS
= 1.2V
85
0
-100
90
100
270
1.475
115
2400
+100
mV
mV
mV
Ω
µA
V
V
mV
mV
V
mV
MΩ
Ω
mA
SYMBOL
I
CC
CONDITIONS
CML inputs and outputs open,
LVDS input V
OS
= 1.2V (Note 2)
MAX3831
MAX3832
MIN
TYP
440
480
MAX
580
614
UNITS
mA
_______________________________________________________________________________________
+3.3V, 2.5Gbps, SDH/SONET, 4-Channel
Interconnect Mux/Demux ICs with Clock Generator
DC ELECTRICAL CHARACTERISTICS (continued)
(V
CC
= +3.0V to +3.6V, LVDS differential load = 100Ω ±1%, CML load = 50Ω ±1% to V
CC
, all TTL inputs are open, T
A
= 0°C to
+85°C, unless otherwise noted. Typical values are at T
A
= +25°C and V
CC
= +3.3V.)
PARAMETER
TTL INPUTS AND OUTPUTS
Input Voltage High
Input Voltage Low
Input Current High
Input Current Low
Output Voltage High
Output Voltage Low
Output Impedance
V
IH
V
IL
I
IH
I
IL
V
OH
V
OL
V
IH
= 2.0V
V
IL
= 0
I
OH
= 20µA
I
OL
= 2mA
TRIEN
= GND
6
-250
-550
2.4
0.4
2.0
0.8
-50
-100
V
V
µA
µA
V
V
kΩ
SYMBOL
CONDITIONS
MIN
TYP
MAX
UNITS
MAX3831/MAX3832
Note 2:
When
TEST
= GND, the pattern generator will consume an additional 30mA.
Note 3:
Guaranteed by design and characterization.
AC ELECTRICAL CHARACTERISTICS
(V
CC
= +3.0V to +3.6V, LVDS differential load = 100Ω ±1%, CML load = 50Ω ±1% to V
CC
, all TTL inputs are open, T
A
= 0°C to
+85°C, unless otherwise noted. Typical values are at T
A
= +25°C and V
CC
= +3.3V.) (Note 4)
PARAMETER
Parallel Input Data Rate
Maximum Parallel Input Skew
Serial-Data Output Rate
Serial-Data Output Rise/Fall Time
Serial-Data Output Random Jitter
Serial-Data Output Deterministic
Jitter
1:4 DEMULTIPLEXER
Serial-Data Input Rate
Serial-Data Setup Time
Serial-Data Hold Time
Parallel-Data Output Rate
Parallel-Clock Output Frequency
PCLKO to PDO_ Delay
LVDS Output Rise/Fall Time
LVDS Differential Skew
LVDS Channel-to-Channel Skew
LVDS Three-State Enable Time
Note 4:
Note 5:
Note 6:
Note 7:
t
SKEW1
t
SKEW2
t
SU
t
H
PDO±
PCLKO±
t
CLK-Q
MAX3831
MAX3832
MAX3831, Figure 3
20% to 80%
Any differential pair
PDO1± to PDO4±
<100
30
-100
Figure 3
Figure 3
100
100
622.08
622.08
155.52
90
300
350
65
2.48832
Gbps
ps
ps
Mbps
MHz
ps
ps
ps
ps
ns
t
r
, t
f
SRJ
SDJ
20% to 80%
(Note 6)
(Note 7)
8
t
es
(Note 5)
SYMBOL
CONDITIONS
MIN
TYP
622.08
±7.5
2.48832
120
3.5
40
18
MAX
UNITS
Mbps
ns
Gbps
ps
ps
RMS
ps
p-p
ps
p-p
4:1 MULTIPLEXER WITH CLOCK GENERATOR
AC characteristics are guaranteed by design and characterization.
Relative to the positive edge of the 155MHz reference clock. PDI1 to PDI4 aligned to RCLKI at reset.
Measured with a reference clock jitter of <1ps
RMS
.
Deterministic jitter is the arithmetic sum of pattern-dependent jitter and pulse-width distortion.
_______________________________________________________________________________________
3
+3.3V, 2.5Gbps, SDH/SONET, 4-Channel
Interconnect Mux/Demux ICs with Clock Generator
MAX3831/MAX3832
PDO+
D
PDO-
V
PDO-
SINGLE-ENDED OUTPUT
V
PDO+
V
OH
R
L
= 100Ω
V
V
OD
|
V
OD
|
V
OS
V
OL
+V
OD
DIFFERENTIAL OUTPUT
0V (DIFF)
0V
-V
OD
V
ODp-p
= V
PDO+
- V
PDO-
Figure 1. Definition of the LVDS Output
SDI+
SDI-
200mV MIN
600mV MAX
(SDI+) - (SDI-)
V
ID
400mVp-p MIN
1200mVp-p MAX
Figure 2. Definition of the CML Input
t
SCLK
= 1 / f
SCLK
SCLKI
t
SU
SDI
t
H
PCLKO
t
CLK-Q
PDO1–PDO4
NOTE:
SIGNAL SHOWN IS DIFFERENTIAL. FOR EXAMPLE, SCLKI = (SCLKI+) - (SCLKI-).
Figure 3. Timing Parameters
4
_______________________________________________________________________________________
+3.3V, 2.5Gbps, SDH/SONET, 4-Channel
Interconnect Mux/Demux ICs with Clock Generator
Typical Operating Characteristics
(V
CC
= +3.3V, T
A
= +25°C, unless otherwise noted.)
SERIAL-DATA OUTPUT EYE DIAGRAM
MAX3831/2 toc01
MAX3831/MAX3832
SERIAL-DATA OUTPUT JITTER
MAX3831/2 toc02
SUPPLY CURRENT vs. TEMPERATURE
MAX3831/2 toc03
600
500
SUPPLY CURRENT (mA)
400
300
200
100
0
MAX3832
MAX3831
2
23
-1 PRBS PATTERN
WIDEBAND RMS
JITTER = 2.48ps
50ps/div
5ps/div
-50
-25
0
25
50
75
100
TEMPERATURE (°C)
ELASTIC STORE RANGE
VARIATION OF DATA DELAY AFTER RESET (ns)
8
6
4
2
0
-2
-4
-6
-8
-10
0
0.2
0.4
0.6
0.8
1.0
1.2
1.4
1.6
DATA TO RCLKI DELAY AT RESET (ns)
-20
-50
CHANNEL ALIGNED TO RCLKI
0
ERROR-FREE OPERATION
MAX3831/2 toc04
SERIAL-DATA HOLD TIME
MAX3831/2 toc05
10
100
80
HOLD TIME (ps)
60
40
20
-25
0
25
50
75
100
TEMPERATURE (°C)
SERIAL-DATA SETUP TIME
MAX3831/2 toc06
MAX3831
PARALLEL CLOCK-TO-DATA OUTPUT
PROPAGATION DELAY vs. TEMPERATURE
PCLKO TO PDO_ PROPAGATION DELAY (ps)
MAX3831/2 toc07
100
80
SETUP TIME (ps)
300
250
200
150
100
50
0
60
40
20
0
-50
-25
0
25
50
75
100
TEMPERATURE (°C)
-50
-25
0
25
50
75
100
TEMPERATURE (°C)
_______________________________________________________________________________________
5
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