19-2709; Rev 1; 5/03
KIT
ATION
EVALU
E
BL
AVAILA
Multirate Clock and Data Recovery
with Limiting Amplifier
General Description
Features
o
Multirate Data Input: 2.667Gbps (FEC), 2.488Gbps,
1.244Gbps, 622.08Mbps, 155.52Mbps,
1.25Gbps/2.5Gbps (Ethernet)
o
Reference Clock Not Required for Data
Acquisition
o
Exceeds ANSI, ITU, and Bellcore SONET/SDH
Jitter Specifications
o
2.7mUI
RMS
Jitter Generation
o
10mV
P-P
Input Sensitivity Without Threshold
Adjust
o
0.65UI
P-P
High-Frequency Jitter Tolerance
o
±170mV
Input Threshold Adjust Range
o
Clock Holdover Capability Using Frequency-
Selectable Reference Clock
o
Serial Loopback Input Available for System
Diagnostic Testing
o
Loss-of-Lock (LOL) Indicator
MAX3872
The MAX3872 is a compact, multirate clock and data
recovery with limiting amplifier for OC-3, OC-12, OC-24,
OC-48, OC-48 with FEC SONET/SDH and Gigabit
Ethernet (1.25Gbps/2.5Gbps) applications. Without using
an external reference clock, the fully integrated phase-
locked loop (PLL) recovers a synchronous clock signal
from the serial NRZ data input. The input data is then
retimed by the recovered clock, providing a clean data
output. An additional serial input (SLBI±) is available for
system loopback diagnostic testing. Alternatively, this
input can be connected to a reference clock to maintain a
valid clock output in the absence of data transitions. The
device also includes a loss-of-lock (LOL) output.
The MAX3872 contains a vertical threshold control to
compensate for optical noise due to EDFAs in DWDM
transmission systems. The recovered data and clock
outputs are CML with on-chip 50Ω back termination on
each line. Its jitter performance exceeds all
SONET/SDH specifications.
The MAX3872 operates from a single +3.3V supply and
typically consumes 580mW. It is available in a 5mm x
5mm 32-pin thin QFN with exposed-pad package and
operates over a -40°C to +85°C temperature range.
Applications
SONET/SDH Receivers and Regenerators
Add/Drop Multiplexers
Digital Cross-Connects
SONET/SDH Test Equipment
DWDM Transmission Systems
Access Networks
Pin Configuration appears at end of data sheet.
PART
MAX3872EGJ
Ordering Information
TEMP RANGE
PIN-PACKAGE
PKG
CODE
G3255-1
-40°C to +85°C 32 QFN
Typical Application Circuit
+3.3V
C
FIL
0.82µF
V
CC
FILTER
OUT+
FIL VCC_VCO CAZ-
SDI+
SDO+
SDO-
CML
+3.3V
CAZ
0.1µF
+3.3V
+3.3V
CAZ+ FREFSET V
CC
MAX3745*
OUT-
IN
GND
+3.3V
SDI-
SLBI+
SLBI-
V
CTRL
MAX3872
SCLKO+
SCLKO-
CML
*FUTURE PRODUCT
SYSTEM
LOOPBACK DATA
V
REF
SIS LREF LOL RS1 RS2 RATESET GND
+3.3V
________________________________________________________________
Maxim Integrated Products
1
For pricing, delivery, and ordering information, please contact Maxim/Dallas Direct! at
1-888-629-4642, or visit Maxim’s website at www.maxim-ic.com.
Multirate Clock and Data Recovery
with Limiting Amplifier
MAX3872
ABSOLUTE MAXIMUM RATINGS
Supply Voltage, V
CC
..............................................-0.5V to +5.0V
Input Voltage Levels
(SDI+, SDI-, SLBI+, SLBI-) ..........(V
CC
- 1.0V) to (V
CC
+ 0.5V)
Input Current Levels
(SDI+, SDI-, SLBI+, SLBI-)............................................±20mA
CML Output Current
(SDO+, SDO-, SCLKO+, SCLKO-) ...............................±22mA
Voltage at
LOL, LREF,
SIS, FIL,
RATESET, FREFSET, RS1, RS2,
V
CTRL
, V
REF
, CAZ+, CAZ-......................-0.5V to (V
CC
+ 0.5V)
Continuous Power Dissipation (T
A
= +85°C)
32-Pin QFN (derate 21.3mW/°C above +85°C) .........1384mW
Operating Junction Temperature Range ...........-55°C to +150°C
Storage Temperature Range .............................-55°C to +150°C
Processing Temperature (die) .........................................+400°C
Lead Temperature (soldering, 10s) .................................+300°C
Stresses beyond those listed under “Absolute Maximum Ratings” may cause permanent damage to the device. These are stress ratings only, and functional
operation of the device at these or any other conditions beyond those indicated in the operational sections of the specifications is not implied. Exposure to
absolute maximum rating conditions for extended periods may affect device reliability.
DC ELECTRICAL CHARACTERISTICS
(V
CC
= +3.0V to +3.6V, T
A
= -40°C to +85°C. Typical values at V
CC
= +3.3V, T
A
= +25°C, unless otherwise noted.) (Note 1)
PARAMETER
Supply Current
Single-Ended Input Voltage
Range
Input Common-Mode Voltage
Input Termination to V
CC
Differential Input Voltage Range
(SDI±)
Threshold Adjustment Range
Threshold Control Voltage
Threshold Control Linearity
Threshold Setting Accuracy
Threshold Setting Stability
Maximum Input Current
Reference Voltage Output
CML Differential Output Swing
CML Differential Output
Impedance
CML Output Common-Mode
Voltage
R
O
(Note 4)
I
CTRL
V
REF
(Note 4)
Figure 2
15mV
≤
|V
TH
|
≤
80mV
80mV < |V
TH
|
≤
170mV
-18
-6
-12
-10
2.14
600
85
2.2
800
100
V
CC
- 0.2
V
TH
V
CTRL
R
IN
SYMBOL
I
CC
(Note 2)
V
CC
- 0.8
V
CC
- 0.4
42.5
50
CONDITIONS
MIN
TYP
175
MAX
215
V
CC
+ 0.4
V
CC
57.5
UNITS
mA
INPUT SPECIFICATIONS (SDI±, SLBI±)
V
IS
Figure 1
Figure 1
V
V
Ω
THRESHOLD-SETTING SPECIFICATIONS (SDI±)
Threshold adjust enabled
Figure 2
Figure 2 (Note 3)
50
-170
0.3
±5
+18
+6
+12
+10
2.24
1000
115
600
+170
2.1
mV
P-P
mV
V
%
mV
mV
µA
V
mV
P-P
Ω
V
CML OUTPUT SPECIFICATIONS (SDO±, SCLKO±)
2
_______________________________________________________________________________________
Multirate Clock and Data Recovery
with Limiting Amplifier
DC ELECTRICAL CHARACTERISTICS (continued)
(V
CC
= +3.0V to +3.6V, T
A
= -40°C to +85°C. Typical values at V
CC
= +3.3V, T
A
= +25°C, unless otherwise noted.) (Note 1)
PARAMETER
LVTTL Input High Voltage
LVTTL Input Low Voltage
LVTTL Input Current
LVTTL Output High Voltage
LVTTL Output Low Voltage
V
OH
V
OL
I
OH
= +20µA
I
OL
= -1mA
SYMBOL
V
IH
V
IL
-10
2.4
0.4
CONDITIONS
MIN
2.0
0.8
+10
TYP
MAX
UNITS
V
V
µA
V
V
MAX3872
LVTTL INPUT/OUTPUT SPECIFICATIONS (LOL,
LREF,
RATESET, RS1, RS2, FREFSET)
Note 1:
Note 2:
Note 3:
Note 4:
At -40°C, DC characteristics are guaranteed by design and characterization.
CML outputs open.
Voltage applied to V
CTRL
pin is from +0.3V to +2.1V when input threshold is adjusted from +170mV to -170mV.
R
L
= 50Ω to V
CC
.
AC ELECTRICAL CHARACTERISTICS
(V
CC
= +3.0V to +3.6V, T
A
= -40°C to +85°C. Typical values are at V
CC
= +3.3V and T
A
= +25°C, unless otherwise noted.) (Note 5)
PARAMETER
Serial Input Data Rate
Differential Input Voltage (SDI±)
Differential Input Voltage (SLBI±)
Jitter Transfer Bandwidth
Jitter Peaking
Sinusoidal Jitter Tolerance
OC-48
J
BW
J
P
V
ID
Threshold adjust disabled, Figure 1 (Note 6)
BER
≤
10
-10
OC-3
OC-12
OC-48
f
≤
J
BW
f = 100kHz
f = 1MHz
f = 10MHz
f = 25kHz
Sinusoidal Jitter Tolerance
OC-12
f = 250kHz
f = 2.5MHz
f = 6.5kHz
Sinusoidal Jitter Tolerance
OC-3
Sinusoidal Jitter Tolerance with
Threshold Adjust Enabled
OC-48 (Note 7)
Jitter Generation
Differential Input Return Loss
(SDI±, SLBI±)
J
GEN
-20log
| S
11
|
f = 65kHz
f = 650kHz
f = 100kHz
f = 1MHz
f = 10MHz
(Note 8)
100kHz to 2.5GHz
2.5GHz to 4.0GHz
3.1
0.62
0.44
2.9
0. 59
0.42
2.9
0.59
0.42
10
50
80
370
1500
8.0
0.93
0.65
8.3
1.03
0.63
7.8
1.05
0.64
7.1
0.82
0.54
2.7
16
15
4.0
mUI
RMS
dB
UI
P-P
UI
P-P
UI
P-P
UI
P-P
SYMBOL
CONDITIONS
MIN
TYP
Table 2
1600
800
130
500
2000
0.1
dB
kHz
mV
P-P
mV
P-P
MAX
UNITS
_______________________________________________________________________________________
3
Multirate Clock and Data Recovery
with Limiting Amplifier
MAX3872
AC ELECTRICAL CHARACTERISTICS (continued)
(V
CC
= +3.0V to +3.6V, T
A
= -40°C to +85°C. Typical values are at V
CC
= +3.3V and T
A
= +25°C, unless otherwise noted.) (Note 5)
PARAMETER
Output Edge Speed
CML Output Differential Swing
Clock-to-Q Delay
Tolerated Consecutive Identical
Digits
Acquisition Time
LOL
Assert Time
Low-Frequency Cutoff for
DC-Offset Cancellation
CLOCK HOLDOVER SPECIFICATIONS
Reference Clock Frequency
Maximum VCO Frequency Drift
(Note 11)
Table 3
400
ppm
t
CLK-Q
PLL ACQUISITION/LOCK SPECIFICATIONS
BER
≤
10
-10
Figure 4 (Note 10)
Figure 4
CAZ = 0.1µF
2.3
4
2000
5.5
100.0
bits
ms
µs
kHz
SYMBOL
t
r
, t
f
20% to 80%
R
C
= 100Ω differential
(Note 9)
600
-50
800
CONDITIONS
MIN
TYP
MAX
110
1000
+50
UNITS
ps
mV
P-P
ps
CML OUTPUT SPECIFICATIONS (SDO±, SCLKO±)
AC characteristics are guaranteed by design and characterization.
Jitter tolerance is guaranteed (BER
≤
10
-10
) within this input voltage range. Input threshold adjust is disabled with VCTRL
connected to V
CC
.
Note 7:
Measured at OC-48 data rate using a 100mV
P-P
differential swing with a 20mVDC offset and an edge speed of 145ps (4th-
order Bessel filter with f
3dB
= 1.8GHz).
Note 8:
Measured with 10mV
P-P
differential input, 2
23
- 1 PRBS pattern at OC-48 with bandwidth from 12kHz to 20MHz.
Note 9:
Relative to the falling edge of the SCLKO+ (Figure 3).
Note 10:
Measured using a 0.82µF loop-filter capacitor initialized to +3.6V.
Note 11:
Measured at OC-48 data rate under
LOL
condition with the CDR clock output set by the external reference clock.
Note 5:
Note 6:
Timing Diagrams
V
CC
+ 0.4V
800mV
V
CC
5mV
V
TH
(mV)
+188
+170
+152
THRESHOLD-SETTING STABILITY
(OVERTEMPERATURE AND POWER SUPPLY)
V
CC
- 0.4V
V
CC
(a) AC-COUPLED SINGLE-ENDED INPUT
5mV
0.3
1.1
1.3
V
CTRL
(V)
2.10
THRESHOLD-
SETTING
ACCURACY
(PART-TO-PART
VARIATION OVER
PROCESS)
800mV
V
CC
- 0.4V
-152
-170
-188
(b) DC-COUPLED SINGLE-ENDED INPUT
V
CC
- 0.8V
Figure 1. Definition of Input Voltage Swing
Figure 2. Relationship Between Control Voltage and Threshold
Voltage
4
_______________________________________________________________________________________
Multirate Clock and Data Recovery
with Limiting Amplifier
MAX3872
Timing Diagrams (continued)
t
CLK
INPUT DATA
SCLKO+
t
CLK-Q
LOL ASSERT TIME
SDO
LOL OUTPUT
ACQUISITION TIME
DATA
DATA
Figure 3. Definition of Clock-to-Q Delay
Figure 4.
LOL
Assert Time and PLL Acquisition Time
Measurement
Typical Operating Characteristics
(V
CC
= +3.3V, T
A
= +25°C, unless otherwise noted.)
RECOVERED CLOCK AND DATA
(2.488Gbps, 2
23
- 1 PATTERN, V
IN
= 10mV
P-P
)
MAX3872toc01
RECOVERED CLOCK AND DATA
(2.67Gbps, 2
23
- 1 PATTERN, V
IN
= 10mV
P-P
)
MAX3872toc02
200mV/
div
200mV/
div
100ps/div
100ps/div
RECOVERED CLOCK JITTER
(2.488Gbps)
MAX3872toc03
RECOVERED CLOCK JITTER
(622.08Mbps)
MAX3872toc04
JITTER GENERATION
vs. POWER-SUPPLY WHITE NOISE
3.5
JITTER GENERATION (ps
RMS
)
3.0
2.5
2.0
1.5
1.0
0.5
0.0
0
5
10
15
20
25
30
OC-48
PRBS = 2
23
- 1
MAX3872toc05
4.0
10ps/div
TOTAL WIDEBAND RMS JITTER = 1.60ps
PEAK-TO-PEAK JITTER = 12.20ps
10ps/div
TOTAL WIDEBAND RMS JITTER = 2.17ps
PEAK-TO-PEAK JITTER = 15.80ps
WHITE-NOISE AMPLITUDE (mV
RMS
)
_______________________________________________________________________________________
5
stm32/stm8
京公网安备 11010802033920号
Copyright © 2005-2026 EEWORLD.com.cn, Inc. All rights reserved
电子工程世界
