DATASHEET
CLOCK SLICER USER CONFIGURABLE PECL INPUT ZERO DELAY BUFFER
ICS527-02
Description
The ICS527-02 Clock Slicer is the most flexible way to
generate a CMOS output clock from a PECL input
clock with zero skew. The user can easily configure the
device to produce nearly any output clock that is
multiplied or divided from the input clock. The part
supports non-integer multiplications and divisions. A
SYNC pulse indicates when the rising clock edges are
aligned with zero skew. Using Phase-Locked Loop
(PLL) techniques, the device accepts an input clock up
to 200 MHz and produces an output clock up to 160
MHz.
The ICS527-02 aligns rising edges on PECLIN with
FBIN at a ratio determined by the reference and
feedback dividers.
For a PECL input and output clock with zero delay, use
the ICS527-04.
For a CMOS input and PECL output with zero delay,
use the ICS527-03.
Features
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Packaged as 28-pin SSOP, Pb-free (150 mil body)
Synchronizes fractional clocks rising edges
PECL IN to CMOS OUT
Pin selectable dividers
Zero input to output skew
User determines the output frequency—no software
needed
Slices frequency or period
Input clock frequency of 1.5 MHz to 200 MHz
Output clock frequencies from 4 MHz to 160 MHz
Very low jitter
Duty cycle of 45/55
Operating voltage of 3.3 V
Advanced, low-power CMOS process
Industrial temperature version available
Block Diagram
R6:R0
7
PECLIN
PECLIN
Reference
Divider
Phase Comparator,
Charge Pump, and
Loop Filter
FBIN
Feedback
Divider
2
VCO
Output
Divider
Divide
by 2
1
0
33 ohm
CLK2
Feedback can
come from
CLK1 or CLK2
(not both)
2
VDD
33 ohm
CLK1
SYNC
7
F6:F0
GND
PDTS
2
S1:S0
DIV2
IDT™ / ICS™
CLOCK SLICER USER CONFIGURABLE PECL INPUT ZERO DELAY BUFFER 1
ICS527-02
REV J 051310
ICS527-02
CLOCK SLICER USER CONFIGURABLE PECL INPUT ZERO DELAY BUFFER
PECL ZDB AND MULTIPLIER/DIVIDER
Pin Assignment
R5
R6
D IV 2
S0
S1
VDD
P E C L IN
P E C L IN
GND
O ECLK2
F0
F1
F2
F3
1
2
3
4
5
6
7
8
9
10
11
12
13
14
28
27
26
25
24
23
22
21
20
19
18
17
16
15
R4
R3
R2
R1
R0
VDD
C LK1
C LK2
GND
PDTS
F B IN
F6
F5
F4
Output Frequency Range Table
S1 S0
0
0
1
1
0
1
0
1
Output Frequency (MHz)
Commercial
10 - 50
5 - 40
4 - 10
20 -160
Industrial
16 - 45
8 - 33
4-8
32 - 140
CLK2 Operation Table
OECLK2
0
1
1
DIV2
X
0
1
CLK2
Z
SYNC
CLK1/2
28-pin 150 mil body SSOP
Pin Descriptions
Pin
Number
1,2, 24-28
3
4, 5
6, 23
7
8
9, 20
10
11-17
18
19
21
22
Pin
Name
R5, R6,
R0-R4
DIV2
S0, S1
VDD
PECLIN
PECLIN
GND
OECLK2
F0-F6
FBIN
PDTS
CLK2
CLK1
Pin
Type
Input
Input
Input
Power
Input
Input
Power
Input
Input
Input
Input
Output
Output
Pin Description
Reference divider word input pins determined by user. Forms a binary number
from 0 to 127. Internal pull-up.
Selects CLK2 function to output a SYNC signal or a divide by 2 of CLK1 based
on the table above. Internal pull-up.
Select pins for output divider determined by user. See table above. Internal
pull-up.
Connect to +3.3 V.
True PECL input clock.
Complementary PECL input clock.
Connect to ground
CLK2 Output Enable. CLK2 tri-stated when low. Internal pull-up.
Feedback divider word input pins determined by user. Forms a binary number
from 0 to 127. Internal pull-up
Feedback clock input
Power Down. Active low. Turns off entire chip when low, both clock outputs are
tri-stated. Internal pull-up.
Output clock 2. Can be SYNC pulse or a low skew divide by 2 of CLK1.
Output clock 1.
IDT™ / ICS™
CLOCK SLICER USER CONFIGURABLE PECL INPUT ZERO DELAY BUFFER 2
ICS527-02
REV J 051310
ICS527-02
CLOCK SLICER USER CONFIGURABLE PECL INPUT ZERO DELAY BUFFER
PECL ZDB AND MULTIPLIER/DIVIDER
External Components
Decoupling Capacitors
As with any high performance mixed-signal IC, the
ICS527-02 must be isolated from system power supply
noise to perform optimally.
Decoupling capacitors of 0.01µF must be connected
between each VDD and the PCB ground plane. The
capacitor must be connected close to the device to
minimize lead inductance.
P E C L IN
P E C L IN
C LK1
C LK2
p h a s e is
in d e t e r m in a te
C LK 1 F eedback
Series Termination Resistor
Clock output traces over one inch should use series
termination. To series terminate a 50Ω trace (a
commonly used trace impedance), place a 33Ω resistor
in series with the clock line, as close to the clock output
pin as possible. The nominal impedance of the clock
output is 20Ω
.
P E C L IN
P E C L IN
C LK1
C LK2
C LK 2 Feedback
Using the ICS527-02 Clock Slicer
First use DIV2 to select the function of the CLK2 output.
If DIV2 is high, a divide by 2, low skew version of CLK1
is present on CLK2. If DIV2 is low, a SYNC pulse is
generated on CLK2. The SYNC pulse goes high
synchronously with the rising edges of PECLIN and
CLK1 that are de-skewed. The SYNC function operates
at CLK1 frequencies up to 66 MHz. If neither CLK1/2 or
a SYNC pulse are required, then CLK2 should be
disabled by connecting OECLK2 to ground. This will
also give the lowest jitter on CLK1.
Next, the feedback scheme should be chosen. If CLK2
is being used as a SYNC pulse, or is tri-stated, then
CLK1 must be connected to FBIN. If CLK2 is selected
to be CLK1/2 (DIV2=1, OECLK2=1) then either CLK1 or
CLK2 must be connected to FBIN. The choice between
CLK1 or CLK2 is illustrated by the following examples
where the device has been configured to generate
CLK1 that is twice the frequency on PECLIN.
Using CLK1 as feedback will always result in
synchronized rising edges between PECLIN and CLK1
if CLK1 is used as feedback. CLK2 could be a falling
edge compared to PECLIN. Therefore, wherever
possible it is recommended to use CLK2 for feedback,
which will synchronize the rising edges of all three
clocks.
More complicated feedback schemes can be used,
such as incorporating multiple output buffers in the
feedback path. An example is given later in the
datasheet. The fundamental property of the ICS527-02
is that it aligns rising edges on PECLIN and FBIN at a
ratio determined by the reference and feedback
dividers.
Set S1 and S0 (page 2) based on the output frequency.
Lastly, the divider settings should be selected. This is
described in the following section.
Determining ICS527-02 Divider Settings
The user has full control in setting the desired output
clock over the range shown in the table on page 2. The
user should connect the divider select input pins directly
to ground (or VDD, although this is not required
IDT™ / ICS™
CLOCK SLICER USER CONFIGURABLE PECL INPUT ZERO DELAY BUFFER 3
ICS527-02
REV J 051310
ICS527-02
CLOCK SLICER USER CONFIGURABLE PECL INPUT ZERO DELAY BUFFER
PECL ZDB AND MULTIPLIER/DIVIDER
because of internal pull-ups) during Printed Circuit
Board layout, so the ICS527-02 automatically produces
the correct clock when mounted on the board. It is also
possible to connect the inputs to parallel I/O ports in
order to switch frequencies.
The output of the ICS527-02 can be determined by the
following simple equation:
S0 and S1 should be selected depending on the
frequency of CLK1. The table on page 2 gives the
ranges.
The dividers are expressed as integers. For example, if
a 50 MHz output on CLK1 is desired from a 40 MHz
input, the reference divider word (RDW) should be 2
and the feedback divider word (FDW) should be 3 which
gives the required 5/4 multiplication. If multiple choices
of dividers are available, then the lowest numbers
should be used. In this example, the output divide (OD)
should be selected to be 2. Then R6:R0 is 0000010,
F6:F0 is 0000011 and S1:S0 is 00. Also, this example
assumes CLK1 is connected to FBIN.
If you need assistance determining the optimum divider
settings, please send an e-mail to
mk-support@icst.com with the desired input clock and
the desired output frequency.
FDW + 2
-
FB Frequency
= Input Frequency
×
-----------------------
RDW + 2
Where:
Reference Divider Word (RDW) = 0 to 127
Feedback Divider Word (FDW) = 0 to 127
FB Frequency is the same as either CLK1 or
CLK2 depending on feedback connection
Also, the following operating ranges should be
observed:
Input Frequency
-
300kHz
<
------------------------------------------
<
20 MHz
RDW + 2
Typical Example
The layout diagram below will produce the waveforms shown on the right.
VDD
R5
R6
DIV2
S0
0.01µF
R4
R3
R2
R1
R0
VDD
CLK1
CLK2
33Ω
33Ω
0.01µF
S1
VDD
40 MHz
PECLIN
40 MHz
40 MHz
PECLIN
PECLIN
GND
OECLK2
F0
F1
F2
F3
50 MHz
SYNC
PECLIN
50 MHz
CLK1
SYNC
CLK2
GND
PDTS
FBIN
F6
F5
F4
Note: The series termination resistor is located before the feedback trace.
IDT™ / ICS™
CLOCK SLICER USER CONFIGURABLE PECL INPUT ZERO DELAY BUFFER 4
ICS527-02
REV J 051310
ICS527-02
CLOCK SLICER USER CONFIGURABLE PECL INPUT ZERO DELAY BUFFER
PECL ZDB AND MULTIPLIER/DIVIDER
Multiple Output Example
In this example, an input clock of 125 MHz is used. Eight copies of 50 MHz are required as are eight copies
of 25 MHz, de-skewed and aligned to the 125 MHz input clock. The following solution uses the
MK74CB217 which has dual 1 to 8 buffers with low pin-to-pin skew.
VDD
R5
R6
DIV2
S0
0.01µF
R4
R3
R2
R1
R0
ICS527-02
0.01µF
INA
QA0
QA1
QA2
VDD
VDD
50M
25M
0.01µF
MK74CB217
INB
QB0
QB1
QB2
VDD
VDD
0.01µF
S1
VDD
VDD
CLK1
CLK2
GND
PDTS
FBIN
F6
F5
F4
125 MHz
125 MHz
PECLIN
PECLIN
GND
OECLK2
F0
F1
F2
F3
QA3
QA4
GND
GND
QA5
QA6
QA7
OEA
QB3
QB4
GND
GND
QB5
QB6
QB7
OEB
The layout design above produces the waveforms shown below. Note: Series terminating resistors are not shown.
125 M H z,
PEC LIN
25 M H z,
Q A0-7
50 M H z,
Q B0-7
P EC LIN not show n
PCB Layout Recommendations
For optimum device performance and lowest output
phase noise, the following guidelines should be
observed.
1) Each 0.01µF decoupling capacitor should be
mounted on the component side of the board as close
to the VDD pin as possible. No via’s should be used
between decoupling capacitor and VDD pin. The PCB
trace to VDD pin should be kept as short as possible, as
should the PCB trace to the ground via.
2) To minimize EMI the 33Ω series termination resistor,
if needed, should be placed close to the clock outputs.
3) An optimum layout is one with all components on the
same side of the board, minimizing vias through other
signal layers. Other signal traces should be routed away
from the ICS527-02. This includes signal traces just
underneath the device, or on layers adjacent to the
ground plane layer used by the device.
IDT™ / ICS™
CLOCK SLICER USER CONFIGURABLE PECL INPUT ZERO DELAY BUFFER 5
ICS527-02
REV J 051310
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