Preliminary
KM688100 Family
Document Title
1Mx8 bit Low Power and Low Voltage CMOS Static RAM
CMOS SRAM
Revision History
Revision No. History
0.0
Initial draft
- Dual CS
Draft Date
June 22, 1999
Remark
Advance
The attached datasheets are provided by SAMSUNG Electronics. SAMSUNG Electronics CO., LTD. reserve the right to change the specifications and
products. SAMSUNG Electronics will answer to yourquestions about device. If you have any questions, please contact the SAMSUNG branch offices.
1
Revision 0.0
June 1999
Preliminary
KM688100 Family
1Mx8 bit Low Power and Low Voltage CMOS Static RAM
FEATURES
•
Process Technology: TFT
•
Organization: 1M x8
•
Power Supply Voltage: 4.5~5.5V
•
Low Data Retention Voltage: 2.0V(Min)
•
Three state output and TTL Compatible
•
Package Type: 44-TSOP2-400F/R
CMOS SRAM
GENERAL DESCRIPTION
The KM688100 families are fabricated by SAMSUNG′s
advanced CMOS process technology. The families support
industrial operating temperature ranges for user flexibility of
system design. The families also support low data retention
voltage for battery back-up operation with low data retention
current.
PRO
DUCT FAMILY
Power Dissipation
Product Family
KM688100L-L
KM688100LI-L
Operating Temperature
Commercial(0~70°C)
Industrial(-40~85°C)
Vcc Range
Speed
Standby
(I
SB1
, Max)
50µA
80µA
Operating
(I
CC2
, Max)
70mA
PKG Type
4.5~5.5V
55
1)
/70ns
44-TSOP2-400F/R
1. The parameter is measured with 50pF test load.
PIN DESCRIPTION
A4
A3
A2
A1
A0
CS1
DNU
DNU
I/O1
I/O2
Vcc
Vss
I/O3
I/O4
DNU
DNU
WE
A19
A18
A17
A16
A15
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
44
43
42
41
40
39
38
37
36
35
34
33
32
31
30
29
28
27
26
25
24
23
A5
A6
A7
OE
CS2
A8
DNU
DNU
I/O8
I/O7
Vss
Vcc
I/O6
I/O5
DNU
DNU
A9
A10
A11
A12
A13
A14
A5
A6
A7
OE
CS2
A8
DNU
DNU
I/O8
I/O7
Vss
Vcc
I/O6
I/O5
DNU
DNU
A9
A10
A11
A12
A13
A14
44
43
42
41
40
39
38
37
36
35
34
33
32
31
30
29
28
27
26
25
24
23
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
A4
A3
A2
A1
A0
CS1
DNU
DNU
I/O1
I/O2
Vcc
Vss
I/O3
I/O4
DNU
DNU
WE
A19
A18
A17
A16
A15
FUNCTIONAL BLOCK DIAGRAM
Clk gen.
Precharge circuit.
Vcc
Vss
Row
Addresses
Row
select
Memory array
1024 rows
1024×8 columns
44-TSOP2
Forward
44-TSOP2
Reverse
I/O
1
~I/O
8
Data
cont
I/O Circuit
Column select
Data
cont
Column Addresses
Name
CS
1
, CS
2
OE
WE
I/O
1
~I/O
8
Function
Chip Select Inputs
Output Enable Input
Write Enable Input
Data Inputs/Outputs
Name
Vcc
Vss
Function
Power
Ground
CS1
CS2
OE
WE
A
0
~A
19
Address Inputs
DNU
Do Not Use
Control Logic
SAMSUNG ELECTRONICS CO., LTD.
reserves the right to change products and specifications without notice.
2
Revision 0.0
June 1999
Preliminary
KM688100 Family
PRODUCT LIST
Commercial Temperature Products(0~70°C)
Part Name
KM688100LT-7L
KM688100LT-10L
KM688100LR-7L
KM688100LR-10L
Function
44-TSOP2-F, 70ns, 5.0V, LL
44-TSOP2-F, 100ns, 5.0V, LL
44-TSOP2-R, 70ns, 5.0V, LL
44-TSOP2-R, 100ns, 5.0V, LL
CMOS SRAM
Industrial Temperature Products(-40~85°C)
Part Name
KM688100LTI-7L
KM688100LTI-10L
KM688100LRI-7L
KM688100LRI-10L
Function
44-TSOP2-F, 70ns, 5.0V, LL
44-TSOP2-F, 100ns, 5.0V, LL
44-TSOP2-R, 70ns, 5.0V, LL
44-TSOP2-R, 100ns, 5.0V, LL
FUNCTIONAL DESCRIPTION
CS
1
H
X
L
L
L
CS
2
X
L
H
H
H
OE
X
X
H
L
X
WE
X
X
H
H
L
I/O
1~8
High-Z
High-Z
High-Z
Dout
Din
Mode
Deselected
Deselected
Output Disabled
Read
Write
Power
Standby
Standby
Active
Active
Active
Note : X means don′t care. (Must be low or high state)
ABSOLUTE MAXIMUM RATINGS
1)
Item
Voltage on any pin relative to Vss
Voltage on Vcc supply relative to Vss
Power Dissipation
Storage temperature
Operating Temperature
Symbol
V
IN
,V
OUT
V
CC
P
D
T
STG
T
A
Ratings
-0.5 to 7.0
-0.3 to 7.0
1.0
-65 to 150
0 to 70
-40 to 85
Unit
V
V
W
°C
°C
°C
Remark
-
-
-
-
KM688100L
KM688100LI
1. Stresses greater than those listed under "Absolute Maximum Ratings" may cause permanent damage to the device. Functional operation should be
restricted to recommended operating condition. Exposure to absolute maximum rating conditions for extended periods may affect reliability.
3
Revision 0.0
June 1999
Preliminary
KM688100 Family
RECOMMENDED DC OPERATING CONDITIONS
1)
Item
Supply voltage
Ground
Input high voltage
Input low voltage
Symbol
Vcc
Vss
V
IH
V
IL
Product
KM688100 Family
All Family
KM688100 Family
KM688100 Family
Min
4.5
0
2.2
-0.5
3)
CMOS SRAM
Typ
5.0
0
-
-
Max
5.5
0
Vcc+0.5
2)
0.8
Unit
V
V
V
V
Note:
1. Commercial Product : T
A
=0 to 70°C, otherwise specified.
Industrial Product : T
A
=-40 to 85°C, otherwise specified.
2. Overshoot: V
CC
+3.0V in case of pulse width
≤30ns.
3. Undershoot: -3.0V in case of pulse width
≤30ns.
4. Overshoot and undershoot are sampled, not 100% tested.
CAPACITANCE
1)
(f=1MHz, T
A
=25°C)
Item
Input capacitance
Input/Output capacitance
1. Capacitance is sampled, not 100% tested.
Symbol
C
IN
C
IO
Test Condition
V
IN
=0V
V
IO
=0V
Min
-
-
Max
8
10
Unit
pF
pF
DC AND OPERATING CHARACTERISTICS
Item
Input leakage current
Output leakage current
Operating power supply current
Symbol
I
LI
I
LO
I
CC
I
CC1
Average operating current
I
CC2
Output low voltage
Output high voltage
Standby Current(TTL)
Standby Current(CMOS)
V
OL
V
OH
I
SB
I
SB1
V
IN
=Vss to Vcc
CS
1
=V
IH,
CS
2
=V
IL
or OE=V
IH
or WE=V
IL
, V
IO
=Vss to Vcc
I
IO
=0mA, CS
1
=V
IL,
CS
2
=V
IH
, WE=V
IH
, V
IN
=V
IH
or V
IL
Cycle time=1µs, 100%duty, I
IO
=0mA, CS
1
≤0.2V,
CS
2
≥Vcc-0.2V,
V
IN
≤0.2V
or V
IN
≥V
CC
-0.2V
Cycle time=Min, I
IO
=0mA, 100% duty, CS
1
=V
IL
, CS
2
=V
IH,
V
IN
=V
IL
or V
IH
I
OL
= 2.1mA
I
OH
= -1.0mA
CS
1
=V
IH
, CS
2
=V
IL
, Other inputs=V
IH
or V
IL
CS≥Vcc-0.2V, Other inputs=0~Vcc
KM688100L-L
KM688100LI-L
2.4
-
-
-
-
-
-
3
50
80
Test Conditions
Min
-1
-1
-
-
-
Typ
-
-
-
-
-
Max
1
1
12
10
70
0.4
Unit
µA
µA
mA
mA
mA
V
V
mA
µA
4
Revision 0.0
June 1999
Preliminary
KM688100 Family
AC OPERATING CONDITIONS
TEST CONDITIONS
(Test Load and Input/Output Reference)
Input pulse level: 0.4 to 2.2V
Input rising and falling time: 5ns
Input and output reference voltage:1.5V
Output load(see right): C
L
=100pF+1TTL
C
L
=50pF+1TTL
CMOS SRAM
C
L
1
)
1.Including scope and jig capacitance
AC CHARACTERISTICS
(V
CC
=4.5~5.5V, Commercial product: T
A
=0 to 70°C, Industrial product: T
A
=-40 to 85°C)
Speed Bins
Parameter List
Symbol
Min
Read cycle time
Address access time
Chip select to output
Output enable to valid output
Read
Chip select to low-Z output
Output enable to low-Z output
Output hold from address change
Chip disable to high-Z output
OE disable to high-Z output
Write cycle time
Chip select to end of write
Address set-up time
Address valid to end of write
Write
Write pulse width
Write recovery time
Write to output high-Z
Data to write time overlap
Data hold from write time
End write to output low-Z
t
RC
t
AA
t
CO1
, t
CO2
t
OE
t
LZ1
, t
LZ1
t
OLZ
t
OH
t
HZ1
, t
HZ1
t
OHZ
t
WC
t
CW1
, t
CW2
t
AS
t
AW
t
WP
t
WR
t
WHZ
t
DW
t
DH
t
OW
55
-
-
-
10
5
5
0
0
10
-
0
55
45
0
45
45
0
0
55ns
Max
-
55
55
25
-
-
-
20
20
-
25
20
-
-
-
-
-
-
20
Min
70
-
-
-
10
5
10
0
0
70
60
0
60
55
0
0
30
0
5
70ns
Max
-
70
70
35
-
-
-
25
25
-
-
-
-
-
-
25
-
-
-
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
Units
DATA RETENTION CHARACTERISTICS
Item
Vcc for data retention
Data retention current
Data retention set-up time
Recovery time
Symbol
V
DR
I
DR
t
SDR
t
RDR
Test Condition
CS
1
≥Vcc-0.2V
1)
Vcc=3.0V, CS
1
≥Vcc-0.2V
1)
See data retention waveform
Min
2.0
-
0
5
Typ
-
-
-
-
Max
5.5
20
2)
-
-
Unit
V
µA
ms
1. CS
1
≥Vcc-0.2V,CS
2
≥
Vcc-0.2V(CS
1
controlled) or CS
2
≥
Vcc-0.2V(CS
2
controlled).
2. Industrial product=30µA
5
Revision 0.0
June 1999
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