IDT5T9820
EEPROM PROGRAMMABLE 2.5V ZERO DELAY PLL CLOCK DRIVER
INDUSTRIAL TEMPERATURE RANGE
EEPROM PROGRAMMABLE
2.5V ZERO DELAY PLL
CLOCK DRIVER
FEATURES:
• 2.5 V
DD
• 5 pairs of outputs
• Low skew: 100ps all outputs at same interface level, 250ps all
outputs at different interface levels
• Selectable positive or negative edge synchronization
• Tolerant of spread spectrum input clock
• Synchronous output enable
• Selectable inputs
• Input frequency: 4.17MHz to 250MHz
• Output frequency: 12.5MHz to 250MHz
• Internal non-volatile EEPROM
• JTAG or I
2
C bus serial interface for programming
• Hot insertable and over-voltage tolerant inputs
• Feedback divide selection with multiply ratios of (1-6, 8, 10, 12)
• Selectable HSTL, eHSTL, 1.8V/2.5V LVTTL, or LVEPECL input
interface
• Selectable HSTL, eHSTL, or 1.8V/2.5V LVTTL output interface for
each output bank
• Selectable differential or single-ended inputs and ten single-
ended outputs
• PLL bypass for DC testing
• External differential feedback, internal loop filter
• Low Jitter: <75ps cycle-to-cycle, all outputs at same interface
level: <100ps cycle-to-cycle all outputs at different interface
levels
• Power-down mode
• Lock indicator
• Available in VFQFPN package
IDT5T9820
DESCRIPTION:
The IDT5T9820 is a 2.5V PLL clock driver intended for high perfor-
mance computing and data-communications applications. The IDT5T9820
has ten outputs in five banks of two, plus a dedicated differential feedback.
The redundant input capability allows for a smooth change over to a
secondary clock source when the primary clock source is absent.
The clock driver can be configured through the use of JTAG/I
2
C program-
ming. An internal EEPROM will allow the user to save and restore the
configuration of the device.
The feedback bank allows divide-by-functionality from 1 to 12 through
the use of JTAG or I
2
C programming. This provides the user with frequency
multiplication 1 to 12 without using divided outputs for feedback. Each output
bank also allows for a divide-by functionality of 2 or 4.
The IDT5T9820 features a user-selectable, single-ended or differential
input to ten single-ended outputs. The clock driver also acts as a translator from
a differential HSTL, eHSTL, 1.8V/2.5V LVTTL, LVEPECL, or single-ended
1.8V/2.5V LVTTL input to HSTL, eHSTL, or 1.8V/2.5V LVTTL outputs. Each
output bank can be individually configured to be either HSTL, eHSTL, 2.5V
LVTTL, or 1.8V LVTTL, including the feedback bank. Also, each clock input
can be individually configured to accept 2.5V LVTTL, 1.8V LVTTL, or
differential signals. The outputs can be synchronously enabled/disabled.
Furthermore, all the outputs can be synchronized with the positive edge
of the REF clock input or the negative edge of REF.
The IDT logo is a registered trademark of Integrated Device Technology, Inc.
INDUSTRIAL TEMPERATURE RANGE
1
c
2004
Integrated Device Technology, Inc.
NOVEMBER 2004
DSC - 6503/24
IDT5T9820
EEPROM PROGRAMMABLE 2.5V ZERO DELAY PLL CLOCK DRIVER
INDUSTRIAL TEMPERATURE RANGE
FUNCTIONAL BLOCK DIAGRAM
TDO/ADDR1
TMS/ADDR0
TCLK/SCLK
TDI/SDA
TRST/SEL
(TDO)
(ADDR1)
JTAG/I2C
PROGRAMMING
SELECTION
AND CONTROL
LOGIC
1sOE
V
DD
Q1
Divide
Select
1
Q
0
1
Q
1
2sOE
EEPROM
Divide
Select
PD
OMODE
FB
FB/V
REF
2
REF0
REF0/V
REF
0
REF1
REF1/V
REF
1
1
0
1
Divide
Select
/N
PLL
0
Divide
Select
V
DD
Q2
2
Q
0
2
Q
1
3sOE
V
DD
Q3
3
Q
0
3
Q
1
4sOE
V
DD
Q4
4
Q
0
4
Q
1
5sOE
REF_SEL
PLL_EN
LOCK(φ)
Divide
Select
V
DD
Q5
5
Q
0
5
Q
1
V
DD
QFB
Divide
Select
QFB
QFB
2
IDT5T9820
EEPROM PROGRAMMABLE 2.5V ZERO DELAY PLL CLOCK DRIVER
INDUSTRIAL TEMPERATURE RANGE
PIN CONFIGURATION
TMS/ADDR0
TDO/ADDR1
V
DD
Q1
V
DD
Q1
V
DD
Q2
LOCK
V
DD
Q2
53
1
Q
0
67
1
Q
1
60
59
64
68
66
65
63
62
61
57
56
58
55
54
52
2sOE
1sOE
V
DD
V
DD
V
DD
V
DD
2
Q
1
2
Q
0
V
DD
TDI/SDA
TCLK/SCLK
V
DD
REF_SEL
REF
1
REF
1
/V
REF1
REF
0
REF
0
/V
REF0
FB
FB/V
REF2
V
DD
V
DD
NC
NC
NC
NC
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
27
33
19
25
18
20
26
21
22
23
24
28
29
30
31
32
34
51
50
49
48
47
46
45
44
GND
43
42
41
40
39
38
37
36
35
TRST/SEL
OMODE
3sOE
V
DD
Q3
V
DD
Q3
3
Q
0
3
Q
1
V
DD
V
DD
V
DD
V
DD
4
Q
1
4
Q
0
V
DD
Q4
V
DD
Q4
4sOE
V
DD
PLL_EN
V
DD
Q5
V
DD
Q5
V
DD
QFB
V
DD
QFB
VFQFPN
TOP VIEW
3
5sOE
QFB
QFB
5
Q
1
V
DD
V
DD
V
DD
V
DD
V
DD
V
DD
5
Q
0
PD
IDT5T9820
EEPROM PROGRAMMABLE 2.5V ZERO DELAY PLL CLOCK DRIVER
INDUSTRIAL TEMPERATURE RANGE
ABSOLUTE MAXIMUM RATINGS
(1)
Symbol
V
I
V
O
V
REF
T
J
T
STG
Description
Voltage
(2)
Input Voltage
Output Voltage
Reference Voltage
(3)
Junction Temperature
Storage Temperature
Max
–0.5 to +3.6
–0.5 to +3.6
–0.5 to V
DDQ
+0.5
–0.5 to +3.6
150
–65 to +165
Unit
V
V
V
V
°C
°C
V
DDQN
, V
DD
Power Supply
CAPACITANCE
(T
A
= +25°C, f = 1MHz, V
IN
= 0V)
Parameter
C
IN
C
OUT
Description
Input Capacitance
Output Capacitance
Min.
2.5
—
Typ.
3
6.3
Max.
3.5
7
Unit
pF
pF
NOTE:
1. Capacitance applies to all inputs except JTAG/I
2
C signals, SEL, ADDR0, and ADDR1.
NOTES:
1. Stresses greater than those listed under ABSOLUTE MAXIMUM RATINGS may cause
permanent damage to the device. This is a stress rating only and functional operation
of the device at these or any other conditions above those indicated in the operational
sections of this specification is not implied. Exposure to absolute maximum rating
conditions for extended periods may affect reliability.
2. V
DDQN
and V
DD
internally operate independently. No power sequencing requirements
need to be met.
3. Not to exceed 3.6V.
RECOMMENDED OPERATING RANGE
Symbol
T
A
V
DD
(1)
V
DDQN
(1)
V
T
Description
Ambient Operating Temperature
Internal Power Supply Voltage
HSTL Output Power Supply Voltage
Extended HSTL and 1.8V LVTTL Output Power Supply Voltage
2.5V LVTTL Output Power Supply Voltage
Termination Voltage
Min.
–40
2.3
1.4
1.65
Typ.
+25
2.5
1.5
1.8
V
DD
V
DDQN
/ 2
Max.
+85
2.7
1.6
1.95
Unit
°C
V
V
V
V
V
NOTE:
1. All power supplies should operate in tandem. If V
DD
or V
DDQN
is at maximum, then V
DDQN
or V
DD
(respectively) should be at maximum, and vice-versa.
PIN DESCRIPTION
Symbol
REF
[1:0]
REF
[1:0]
/
V
REF
[1:0]
I/O
I
I
Type
Adjustable
(1)
Adjustable
(1)
Description
Clock input. REF
[1:0]
is the "true" side of the differential clock input. If operating in single-ended mode, REF
[1:0]
is the clock input.
Complementary clock input.
REF
[1:0]
/V
REF
[1:0]
is the "complementary" side of REF
[1:0]
if the input is in differential mode. If operating
in single-ended mode,
REF
[1:0]
/V
REF
[1:0]
is left floating. For single-ended operation in differential mode,
REF
[1:0]
/V
REF
[1:0]
should be set
to the desired toggle voltage for REF
[1:0]
:
2.5V LVTTL
V
REF
= 1250mV (SSTL2 compatible)
1.8V LVTTL, eHSTL
V
REF
= 900mV
HSTL
V
REF
= 750mV
LVEPECL
V
REF
= 1082mV
Clock input. FB is the "true" side of the differential feedback clock input. If operating in single-ended mode, FB is the feedback clock input.
Complementary feedback clock input.
FB/V
REF
2
is the "complementary" side of FB if the input is in differential mode. If operating in single-
ended mode,
FB/V
REF
2
is left floating. For single-ended operation in differential mode,
FB/V
REF
2
should be set to the desired toggle voltage
for FB:
2.5V LVTTL
V
REF
= 1250mV (SSTL2 compatible)
1.8V LVTTL, eHSTL
V
REF
= 900mV
HSTL
V
REF
= 750mV
LVEPECL
V
REF
= 1082mV
FB
FB/V
REF
2
I
I
Adjustable
(1)
Adjustable
(1)
NOTE:
1. Inputs are capable of translating the following interface standards. User can select between:
Single-ended 2.5V LVTTL levels
Single-ended 1.8V LVTTL levels
or
Differential 2.5V/1.8V LVTTL levels
Differential HSTL and eHSTL levels
Differential LVEPECL levels
4
IDT5T9820
EEPROM PROGRAMMABLE 2.5V ZERO DELAY PLL CLOCK DRIVER
INDUSTRIAL TEMPERATURE RANGE
PIN DESCRIPTION, CONTINUED
Symbol
REF_SEL
nsOE
I/O
I
I
Type
LVTTL
(1)
LVTTL
(1)
Description
Reference clock select. When LOW, selects REF
0
and
REF
0
/V
REF
0.
When HIGH, selects REF
1
and
REF
1
/V
REF
1.
Synchronous output enable/disable. Each outputs's enable/disable state can be controlled either with the
nsOE
pin or through JTAG
or I
2
C programming, corresponding bits 52 - 56. When the
nsOE
is HIGH or the corresponding Bit (52 - 56) is 1, the output will be
synchronously disabled. When the
nsOE
is LOW and the corresponding Bit (52 - 56) is 0, the output will be enabled. (See JTAG/I
2
C
Serial Configuration table.)
Feedback clock output
Complementary feedback clock output
Five banks of two outputs
PLL enable/disable control. The PLL's enable/disable state can be controlled either with the
PLL_EN
pin or through JTAG or I
2
C
programming, corresponding Bit 57. When
PLL_EN
is HIGH or the corresponding Bit 57 is 1, the PLL is disabled and REF
[1:0]
goes
to all outputs. When
PLL_EN
is LOW and the corresponding Bit 57 is 0, the PLL will be active.
Power down control. When
PD
is LOW, the inputs are disabled and internal switching is stopped. The OMODE pin in conjunction
with the corresponding Bit 59 selects whether the outputs are gated LOW/HIGH or tri-stated. When OMODE is HIGH or Bit 59 is 1,
Bit 58 determines the level at which the outputs stop. When Bit 58 is 0/1, the nQ
[1:0]
and QFB are stopped in a HIGH/LOW state, while
the
QFB
is stopped in a LOW/HIGH state. When OMODE is LOW and Bit 59 is 0, the outputs are tri-stated. Set
PD
HIGH for normal
operation. (See JTAG/I
2
C Serial Configuration table.)
PLL lock indication signal. HIGH indicates lock. LOW indicates that the PLL is not locked and outputs may not be synchronized to
the inputs. The output will be 2.5V LVTTL. (For more information on application specific use of the LOCK pin, please see AN237.)
OMODE
I
LVTTL
(1)
Output disable control. Used in conjunction with
nsOE
and
PD.
The outputs' disable state can be controlled either with the OMODE
pin or through JTAG or I
2
C programming, corresponding Bit 59. When OMODE is HIGH or the corresponding Bit 59 is 1, the outputs'
disable state will be gated and Bit 58 will determine the level at which the outputs stop. When Bit 58 is 0/1, the nQ
[1:0]
and QFB are
stopped in a HIGH/LOW state, while the
QFB
is stopped in a LOW/HIGH state. When OMODE is LOW and its corresponding bit
59 is 0, the outputs disable state will be the tri-state. (See JTAG/I
2
C Serial Configuration table.)
TRST-
Active LOW input to asynchronously reset the JTAG boundary-scan circuit.
SEL - Select programming interface control for the dual-function pins. When HIGH, the dual-function pins are set for JTAG programming.
When LOW, the dual-function pins are set for I
2
C programming and the JTAG interface is asynchronously placed in the Test Logic Reset
state.
QFB
QFB
nQ
[1:0]
PLL_EN
O
O
O
I
Adjustable
(2)
Adjustable
(2)
Adjustable
(2)
LVTTL
(1)
PD
I
LVTTL
(1)
LOCK
O
LVTTL
TRST/SEL
I/I
LVTTL/
LVTTL
(4,5)
TDO/ADDR1
O/I
LVTTL/
TDO - Serial data output pin for instructions as well as test and programming data. Data is shifted in on the falling edge of TCLK. The
3-Level
(3,4,5)
pin is tri-stated if data is not being shifted out of the device.
ADDR1 - Used to define a unique I
2
C address for this device. Only for I
2
C programming. (See JTAG/I
2
C Serial Interface Description.)
LVTTL/
TMS - Input pin that provides the control signal to determine the transitions of the JTAG TAP controller state machine. Transitions within
3-Level
(3,4,5)
the state machine occur at the rising edge of TCLK. Therefore, TMS must be set up before the rising edge of TCLK. TMS is evaluated
on the rising edge TCLK.
ADDR0 - Used to define a unique I
2
C address for this device. Only for I
2
C programming. (See JTAG/I
2
C Serial Interface Description.)
LVTTL/
LVTTL
(4,5)
LVTTL/
LVTTL
(4,5)
PWR
PWR
PWR
TCLK - The clock input to the JTAG BST circuitry
SCLK - Serial clock for I
2
C programming
TDI - Serial input pin for instructions as well as test and programming data. Data is shifted in on the rising edge of TCLK.
SDA - Serial data for I
2
C programming. (See JTAG/I
2
C Serial Description table.)
Power supply for each pair of outputs. When using 2.5V LVTTL, 1.8V LVTTL, HSTL, or eHSTL outputs, V
DDQN
should be set to its
corresponding outputs (see Front Block Diagram). When using 2.5V LVTTL outputs, V
DDQN
should be connected to V
DD.
Power supply for phase locked loop, lock output, inputs, and other internal circuitry
Ground
TMS/ADDR0
I/I
TCLK/SCLK
TDI/SDA
V
DDQN
V
DD
GND
I/I
I/I
NOTES:
1. Pins listed as LVTTL inputs can be configured to accept 1.8V or 2.5V signals through the use of the I
2
C/JTAG programming, bit 61. (See JTAG/I
2
C Serial Description.)
2. Outputs are user selectable to drive 2.5V, 1.8V LVTTL, eHSTL, or HSTL interface levels when used with the appropriate V
DDQN
voltage.
3. 3-level inputs are static inputs and must be tied to V
DD
or GND or left floating. These inputs are not hot-insertable or over voltage tolerant.
4. The JTAG (TDO, TMS, TCLK, and TDI) and I
2
C (ADDR1, ADDR0, SCLK, and SDA) signals share the same pins (dual-function pins) for which the
TRST/SEL
pin will select between
the two programming interfaces.
5. JTAG and I
2
C pins accept 2.5V signals. The JTAG input pins (TMS, TCLK, TDI,
TRST)
will also accept 1.8V signals.
5
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