Notes: 1. Device linearity will begin to degrade below 10 MHz
2. The DC transient at the output of any port of the switch when the control voltage is switched from Low to High or High to Low in a 50Ω test set-up, measured with
1ns risetime pulses and 500 MHz bandwidth.
Document No. DOC-30006-2
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et
e
Figure 2. Package Type
8-lead MSOP
PE4244
Product Specification
Figure 3. Pin Configuration (Top View)
V
DD
1
2
8
7
RF1
Table 3. Absolute Maximum Ratings
Symbol
V
DD
Parameter/Conditions
Power supply voltage
Voltage on any input
Storage temperature range
Operating temperature
Input power (50Ω)
ESD voltage (Human Body
Min
-0.3
-0.3
-65
-40
Max
4.0
V
DD
+
150
85
30
1500
Units
V
V
°C
°C
dBm
V
CTRL
GND
4244
GND
RFC
3
4
6
5
GND
V
I
T
ST
T
OP
P
IN
V
ESD
RF2
Table 2. Pin Descriptions
Pin No.
1
Pin Name
V
DD
Description
Nominal 3V supply connection. A bypass
capacitor (100 pF) to the ground plane
should be placed as close as possible to
the pin
CMOS logic level:
High = RFC to RF1 signal path
Low = RFC to RF2 signal path
Ground connection. Traces should be
physically short and connected to ground
Common RF port for switch (Note 1)
RF2 port (Note 1)
3
GND
ol
4
5
6
RFC
RF2
GND
et
Control Voltage
Table 4. DC Electrical Specifications
Parameter
Min
2.7
Typ
3.0
250
0.7xV
DD
0.3xV
DD
Max
3.3
500
Units
V
nA
V
V
bs
Ground Connection. Traces should be
physically short and connected to ground
Ground Connection. Traces should be
physically short and connected to ground
RF1 port (Note 1)
V
DD
Power Supply Voltage
I
DD
Power Supply Current
V
DD
= 3V, V
CNTL
= 3V
Control Voltage High
Control Voltage Low
7
GND
8
RF1
O
Note 1: All RF pins must be DC blocked with an external series
capacitor or held at 0 V
DC
Electrostatic Discharge (ESD) Precautions
When handling this UltraCMOS
®
device, observe
the same precautions that you would use with
other ESD-sensitive devices. Although this device
contains circuitry to protect it from damage due to
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