73S8009R
Low Cost Versatile Smart Card
Interface
Simplifying System Integration™
DS_8009R_056
APPLICATIONS
•
DESCRIPTION
The 73S8009R is a very low-cost level shifter, single
smart card (ICC) interface IC. The device includes a
level shifter interface between a 3.3 V (typical) logic
circuitry (host microcontroller) and an ISO-7816 /
EMV smart card. The 73S8009R is designed to
provide full electrical compliance with ISO-7816-3
EMV4.1 (EMV2000) and GSM11-11 specifications.
In normal operating mode, for maximum designer
flexibility, the host microcontroller is responsible for
card activation and deactivation. The 73S8009R
incorporates an ISO-7816-3 deactivation sequencer
that controls the card signals in case of fault detection
and card removal. Card presence and faults are
reported to the host through an interrupt output.
When the 73S8009R is ready to support a card with
the selected voltage, a RDY signal informs the host it
can initiate the card activation sequence.
The 73S8009R supports 5V, 3V and 1.8V cards.
Selection is done through 2 dedicated digital inputs.
Level-shifters drive the card signals with the selected
card voltage coming from an internal Low Drop-Out
(LDO) voltage regulator. The LDO regulator is
powered by a dedicated power supply input, VPC.
Digital circuitry is separately powered by a digital
power supply, VDD.
Emergency card deactivation is initiated upon card
extraction or any fault generated by the protection
circuitry. The fault can be a card over-current, a VDD
(digital power), a VPC (regulator power), a VCC
(card power output) or an over-heating fault.
A chip select digital input drives internal latches that
allow the host controller to control multiple
73S8009R ICs in parallel. A power down digital
input also allows the host microcontroller to place
the IC in a very low-power mode making the
73S8009R particularly suitable for low-power and
battery-powered applications.
Auxiliary I/O lines are also available (SO28 package
only) and make the 73S8009R suitable for all kind
of cards, including synchronous (memory) cards.
Rev. 1.3
•
•
•
Set-Top-Box Conditional Access and
Pay-per-View
SIM card readers in DECT and GSM phones,
GPRS, WIFI and VOIP devices
DATA SHEET
October 2009
Point of Sales & Transaction Terminals
General purpose smart card readers
ADVANTAGES
•
Lowest cost smart card interface IC on the
market
Ideal to replace discrete designs in POS
terminals and Set-Top-Boxes
Traditional step-up converter is replaced by
an LDO regulator
Greatly reduced power dissipation
Fewer external components are required
Better noise performance
Very low power dissipation
Small format (4x4x0.8 mm) QFN20 package
option
•
•
FEATURES
•
Card Interface:
•
Complies with ISO-7816-3, EMV 4.0 and
GSM 11-11 specifications
•
An LDO voltage regulator provides 1.8V /
3V / 5V to the card from an external power
supply input
•
Provides at least 90 mA to the card
•
ISO-7816-3 card emergency deactivation
sequencer
•
Protection includes 3 voltage supervisors
that detect voltage drops on V
CC
(card), V
DD
(digital) and V
PC
(regulator) power supplies
•
Over-current detection, 150 mA max.
•
2 card detection inputs, 1 for each user
polarity
•
Auxiliary I/O lines for C4 / C8 contact
signals
•
Card CLK clock frequency up to 20 MHz
© 2009 Teridian Semiconductor Corporation
1
73S8009R Data Sheet
•
System Controller Interface
•
Five signal images of the card signals
(RSTIN, CLKIN, IOUC, AUX1UC, AUX2UC)
•
Two inputs select card voltage (CMDVCC%,
CMDVCC#)
•
Two Interrupt outputs (OFF, RDY) inform the
system controller of card presence / faults
and the interface status
•
Chip select input (CS)
•
Power down input (PWRDN)
•
DS_8009R_056
Regulator Power Supply (V
PC
):
•
Class A-B-C readers: 5V, 3V and 1.8V
cards: 4.75 V to 6.0 V
Digital Interface (V
DD
): 2.7 V to 3.6 V
6 kV ESD protection on the card interface
SO28 or QFN20 package
•
•
•
FUNCTIONAL DIAGRAM
VDD
[17]
28
VPC
[9]
15
VCC FAULT
VOLTAGE REFERENCE
bias currents
VPC FAULT
vref
LDO
REGULATOR
20
[12]
22
[14]
VCC
GND
CMDVCC5
CMDVCC3
8
[2]
9
[3]
4
[20]
OFF
RDY
PWRDN
CS
10
[4]
RSTIN
11
[5]
CLKIN
12
[6]
13
[7]
1
[18]
CONTROL
LOGIC
RESET
BUFFER
21
[13]
RST
CLOCK
BUFFER
19
[11]
CLK
26
[16]
16
[10]
PRES
PRES
1.5MHz
TEMP FAULT
R-C
OSC.
5
[1]
IOUC
AUX1UC
AUX2UC
6
7
OVER
TEMP
25
[15]
I/O
AUX1
AUX2
SMART CARD I/O BUFFERS
24
23
27
GND
Pin numbers reference the SO28 package
[Pin numbers]
reference the QFN20 Package
Figure 1: 73S8009R Block Diagram
Rev. 1.3
2
DS_8009R_056
73S8009R Data Sheet
Table of Contents
1
2
Pinout ............................................................................................................................................. 5
Electrical Specifications................................................................................................................ 8
2.1 Absolute Maximum Ratings ..................................................................................................... 8
2.2 Recommended Operating Conditions ...................................................................................... 8
2.3 Smart Card Interface Requirements ........................................................................................ 9
2.4 Digital Signals Characteristics ............................................................................................... 11
2.5 DC Characteristics ................................................................................................................ 11
2.6 Voltage / Temperature Fault Detection Circuits...................................................................... 12
Applications Information ............................................................................................................. 13
3.1 Example 73S8009R Schematics ........................................................................................... 13
3.2 System Controller Interface ................................................................................................... 14
3.3 Power Supply and Voltage Supervision ................................................................................. 14
3.4 Card Power Supply ............................................................................................................... 14
3.5 Over-temperature Monitor ..................................................................................................... 15
3.6 Activation and Deactivation Sequence................................................................................... 15
3.7
OFF
and Fault Detection ....................................................................................................... 16
3.8 Power-down Operation.......................................................................................................... 17
3.9 Chip Select ........................................................................................................................... 18
3.10 I/O Circuitry and Timing......................................................................................................... 18
Mechanical Drawings .................................................................................................................. 20
4.1 20-pin QFN ........................................................................................................................... 20
4.2 28-Pin SO ............................................................................................................................. 21
Ordering Information ................................................................................................................... 22
Related Documentation ............................................................................................................... 22
Contact Information..................................................................................................................... 22
3
4
5
6
7
Revision History .................................................................................................................................. 23
Rev. 1.3
3
73S8009R Data Sheet
DS_8009R_056
Figures
Figure 1: 73S8009R Block Diagram ......................................................................................................... 2
Figure 2: 73S8009R 20-Pin QFN Pinout .................................................................................................. 5
Figure 3: 73S8009R 28-Pin SO Pinout..................................................................................................... 5
Figure 4: Typical 73S8009R Application Schematic ............................................................................... 13
Figure 5: Activation Sequence ............................................................................................................... 15
Figure 6: Deactivation Sequence ........................................................................................................... 16
Figure 7: OFF Activity Outside and Inside a Card Session ..................................................................... 17
Figure 8: Power-down Operation ........................................................................................................... 17
Figure 9: CS Timing Definitions.............................................................................................................. 18
Figure 10: I/O and I/OUC State Diagram ................................................................................................ 19
Figure 11: I/O to I/OUC Delay Timing Diagram....................................................................................... 19
Figure 12: 20-pin QFN Package Dimensions ......................................................................................... 20
Figure 13: 28-Pin SO Package Dimensions ........................................................................................... 21
Tables
Table 1: 73S8009R Pin Definitions .......................................................................................................... 6
Table 2: Absolute Maximum Device Ratings ............................................................................................ 8
Table 3: Recommended Operating Conditions ......................................................................................... 8
Table 4: DC Smart Card Interface Requirements ..................................................................................... 9
Table 5: Digital Signals Characteristics .................................................................................................. 11
Table 6: DC Characteristics ................................................................................................................... 11
Table 7: Voltage / Temperature Fault Detection Circuits......................................................................... 12
Table 8: Choice of VCC Pin Capacitor ................................................................................................... 15
Table 9: Order Numbers and Packaging Marks ...................................................................................... 22
4
Rev. 1.3
DS_8009R_056
73S8009R Data Sheet
1 Pinout
The 73S8009R is supplied as a 20-pin QFN package and as a 28-pin SO package.
TEST1
PRES
16
15
14
OFF
20
19
18
CS
I/OUC
CMDVCC%
CMDVCC#
RSTIN
CLKIN
1
2
3
4
5
17
VDD
I/O
VCC
RST
GND
CLK
TERIDIAN
73S8009R
13
12
11
PWRDN
TEST2
RDY
VPC
Figure 2: 73S8009R 20-Pin QFN Pinout
(Top View)
CS
TEST1
N/C
OFF
I/OUC
AUX1UC
AUX2UC
CMDVCC%
CMDVCC#
RSTIN
CLKIN
RDY
PWRDN
TEST2
1
2
3
4
5
6
7
8
9
10
11
12
13
14
28
27
26
25
24
23
22
21
20
19
18
17
16
15
PRES
VDD
GND
PRES
I/O
AUX1
AUX2
VCC
RST
GND
CLK
N/C
N/C
PRES
VPC
Figure 3: 73S8009R 28-Pin SO Pinout
Rev. 1.3
10
6
7
8
9
5
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