CDCM7005-SP
www.ti.com
........................................................................................................................................................
SGLS390A – JULY 2009 – REVISED AUGUST 2009
3.3-V HIGH PERFORMANCE RAD-TOLERANT CLASS V, CLOCK SYNCHRONIZER AND
JITTER CLEANER
1
FEATURES
High Performance LVPECL and LVCMOS PLL
Clock Synchronizer
Two Reference Clock Inputs (Primary and
Secondary Clock) for Redundancy Support
With Manual or Automatic Selection
Accepts LVCMOS Input Frequencies Up to 200
MHz
VCXO_IN Clock is Synchronized to One of the
Two Reference Clocks
VCXO_IN Frequencies Up to 2 GHz (LVPECL)
Outputs Can Be a Combination of LVPECL and
LVCMOS (Up to Five Differential LVPECL
Outputs or Up to 10 LVCMOS Outputs)
Output Frequency is Selectable by x1, /2, /3, /4,
/6, /8, /16 on Each Output Individually
Efficient Jitter Cleaning From Low PLL Loop
Bandwidth
Low Phase Noise PLL Core
Programmable Phase Offset (PRI_REF and
SEC_REF to Outputs)
Wide Charge Pump Current Range From
200
µA
to 3 mA
Dedicated Charge Pump Supply (VCC_CP) for
Wide Tuning Voltage Range VCOs
Presets Charge Pump to VCC_CP/2 for Fast
Center Frequency Setting of VC(X)O
Analog and Digital PLL Lock Indication
Provides VBB Bias Voltage Output for
Single-Ended Input Signals (VCXO_IN)
Frequency Hold Over Mode Improves Fail-Safe
Operation
Power-Up Control Forces LVPECL Outputs to
3-State at V
CC
< 1.5 V
SPI Controllable Device Setting
3.3-V Power Supply
High-Performance 52 Pin Ceramic Quad Flat
•
•
•
•
•
Pack (HFG)
Rad-Tolerant : 25 kRad (Si) TID
QML-V Qualified, SMD 5962-07230
Military Temperature Range (–55°C to 125°C
T
case
)
•
•
•
•
PIN ASSIGNMENTS
GND
STATUS_REF or PRI_SEC_CLK
STATUS_VCXO or I_REF_CP
HFG PACKAGE
(TOP VIEW)
GND
VCC
VCC
VCC
VCC
•
•
•
•
•
•
•
•
•
•
•
•
•
GND
CTRL_DATA
AVCC
CTRL_CLK
CTRL_LE
1
2
3
4
5
6
7
8
9
10
11
12
13
52 51 50 49 48 47 46 45 44 43 42 41 40
Y4B
Y4A
VCC
•
PLL_LOCK
RESET or HOLD
39
38
37
36
35
VCC
Y3B
Y3A
VCC
VCC
Y2B
Y2A
VCC
VCC
Y1B
Y1A
VCC
PD
AVCC
GND
CP_OUT
AVCC
VCC_CP
GND
REF_SEL
GND
34
33
32
31
30
29
28
27
14 15 16 17 18 19 20 21 22 23 24 25 26
SEC_REF
PRI_REF
AVCC
AVCC
VCXO_IN
VCXO_IN
VBB
VCC
VCC
VCC
Y0A
1
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of Texas
Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.
PRODUCTION DATA information is current as of publication date.
Products conform to specifications per the terms of the Texas
Instruments standard warranty. Production processing does not
necessarily include testing of all parameters.
Copyright © 2009, Texas Instruments Incorporated
Y0B
VCC
CDCM7005-SP
SGLS390A – JULY 2009 – REVISED AUGUST 2009
........................................................................................................................................................
www.ti.com
DESCRIPTION
The CDCM7005 is a high-performance, low phase noise and low skew clock synchronizer that synchronizes a
VCXO (voltage controlled crystal oscillator) or VCO (voltage controlled oscillator) frequency to one of the two
reference clocks. The programmable pre-divider M and the feedback-dividers N and P give a high flexibility to the
frequency ratio of the reference clock to VC(X)O:
•
VC(X)O_IN / PRI_REF = (N x P) / M or
•
VC(X)O_IN / SEC_REF = (N x P) / M
VC(X)O_IN clock operates up to 2 GHz. Through the selection of external VC(X)O and loop filter components,
the PLL loop bandwidth and damping factor can be adjust to meet different system requirements.
The CDCM7005 can lock to one of two reference clock inputs (PRI_REF and SEC_REF), supports frequency
hold-over mode and fast-frequency-locking for fail-safe and increased system redundancy. The outputs of the
CDCM7005 are user definable and can be any combination of up to five LVPECL outputs or up to 10 LVCMOS
outputs. The LVCMOS outputs are arranged in pairs (Y0A:Y0B, Y1A:Y1B, …), so that each pair has the same
frequency. But each output can be separately inverted and disabled. The built in synchronization latches ensure
that all outputs are synchronized for low output skew.
All device settings, like outputs signaling, divider value, input selection, and many more, are programmable by
SPI (3-wire serial peripheral interface). SPI allows individually control of the device settings.
The device operates in a 3.3-V environment and is characterized for operation from –55°C to 125°C (T
case
).
ORDERING INFORMATION
(1)
TEMPERATURE
-55°C to 125°C T
case
(1)
(2)
PACKAGE
(2)
52 / HFG
ORDERABLE PART NUMBER
5962-0723001VXC
TOP-SIDE MARKING
5962-0723001VXC
CDCM7005HFG-V
For the most current package and ordering information, see the Package Option Addendum at the end of this document, or see the TI
website at www.ti.com.
Package drawings, thermal data, and symbolization are available at www.ti.com/packaging.
2
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Copyright © 2009, Texas Instruments Incorporated
CDCM7005-SP
www.ti.com
........................................................................................................................................................
SGLS390A – JULY 2009 – REVISED AUGUST 2009
FUNCTIONAL BLOCK DIAGRAM
VCC
AVCC
VCC_CP
Selected REF Signal
STATUS_REF/
PRI_SEC_CLK
STATUS_VCXO/
I_REF_CP
PLL_LOCK
REF_SEL
Manual &
Automatic
CLK Select
freq. Detect
> 2 Mhz
freq. Detect
> 2 Mhz
PRI_REF
R EF_M UX
LVCMOS
SEC_REF
Progr. Delay
M
Progr. Divider
M 2
10
LOCK
HOLD
Reference
Clock
Feedback
Clock
Progr. Delay
N
Progr. Divider
N 2
12
PFD
Charge
Pump
CP_OUT
CTRL_LE
CTRL_DATA
CTRL_CLK
SPI LOGIC
Current
Reference
PECL
to
LVCMOS
Y0_MUX
LV
CMOS
Y0A
PD
RESET or
HOLD
FB_MUX
LV
PECL
Y0B
LV
CMOS
LV
CMOS
Y1A
Y1_MUX
÷1
LV
PECL
Y1B
LV
CMOS
÷2
÷3
LV
CMOS
÷4
VCXO_IN
VCXO_IN
PECL
INPUT
Y2_MUX
LV
PECL
Y2B
LV
CMOS
Y2A
÷6
/8
÷8
÷ 16
÷4
90o 90o
LV
CMOS
Y3A
Y3_MUX
LV
PECL
Y3B
LV
CMOS
÷8
P16-Div
P Divider
Bias Generator
VBB
V
CC
– 1.3V
Y4_MUX
LV
CMOS
Y4A
LV
PECL
Y4B
LV
CMOS
GND
B0057-01
Copyright © 2009, Texas Instruments Incorporated
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CDCM7005-SP
SGLS390A – JULY 2009 – REVISED AUGUST 2009
........................................................................................................................................................
www.ti.com
Table 1. PIN ASSINGMENT
TERMINAL
NAME
HFG
19, 22,
23, 26,
28, 31,
32, 35,
36, 39,
41, 44,
46, 47,
48
Thermal
pad, and
Pins: 1, 7,
11, 13, 45,
51
3, 6, 9
16, 17
10
5
4
2
I/O
DESCRIPTION
VCC
Power
3.3-V supply. There is no internal connection between V
CC
and AV
CC
. It is
recommended that AV
CC
use its own supply filter.
GND
Ground
Ground
AVCC
VCC_CP
CTRL_LE
CTRL_CLK
CTRL_DATA
Analog
Power
Power
I
I
I
3.3-V analog power supply. There is no internal connection between AV
CC
and V
CC
. It is
recommended that AV
CC
use its own supply filter.
This is the charge pump power supply pin used to have the same supply as the external
VCO. It can be set from 2.3 V to 3.6 V.
LVCMOS input, control latch enable for serial programmable Interface (SPI), with
hysteresis
LVCMOS input, serial control clock input for SPI, with hysteresis
LVCMOS input, serial control data input for SPI, with hysteresis
LVCMOS input, asynchronous power down (PD) signal. This pin is low active and can
be activated external or by the corresponding bit in the SPI register (in case of logic
high, the SPI setting is valid). Switches the device into power-down mode. Resets M-
and N-Divider, 3-states charge pump, STATUS_REF, or PRI_SEC_CLK pin,
STATUS_VCXO or I_REF_CP pin, PLL_LOCK pin, VBB pin and all Yx outputs. Sets the
SPI register to default value; has internal 150-kΩ pullup resistor.
This LVCMOS input can be programmed (SPI) to act as HOLD or RESET. RESET is the
default function. This pin is low active and can be activated external or via the
corresponding bit in the SPI register. In case of RESET, the charge pump (CP) is
switched to 3-state and all counters (N, M, P) are reset to zero (the initial divider settings
are maintained in SPI registers). The LVPECL outputs are static low and high
respectively and the LVCMOS outputs are all low or high if inverted. RESET is not edge
triggered and should have a pulse duration of at least 5 ns.
In case of HOLD, the CP is switched in to 3-state mode only. After HOLD is released
and with the next valid reference clock cycle the charge pump is switched back in to
normal operation (CP stays in 3-state as long as no reference clock is valid). During
HOLD, the P divider and all outputs Yx are at normal operation. This mode allows an
external control of the frequency hold-over mode.
The input has an internal 150-kΩ pullup resistor.
PD
27
I
RESET or
HOLD
40
I
VCXO_IN
VCXO_IN
PRI_REF
SEC_REF
21
20
14
15
I
I
I
I
VCXO LVPECL input
Complementary VCXO LVPECL input
LVCMOS input for the primary reference clock, with an internal 150-kΩ pullup resistor
and input hysteresis.
LVCMOS input for the secondary reference clock, with an internal 150-kΩ pullup resistor
and input hysteresis.
LVCMOS reference clock selection input. In the manual mode the REF_SEL signal
selects one of the two input clocks:
REF_SEL [1]: PRI_REF is selected;
REF_SEL [0]: SEC_REF is selected;
The input has an internal 150-kΩ pullup resistor.
Charge pump output
Bias voltage output to be used to bias unused complementary input VCXO_IN for single
ended signals. The output of VBB is V
CC
– 1.3 V. The output current is limited to about
1.5 mA.
REF_SEL
12
I
CP_OUT
VBB
8
18
O
O
4
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CDCM7005-SP
www.ti.com
........................................................................................................................................................
SGLS390A – JULY 2009 – REVISED AUGUST 2009
Table 1. PIN ASSINGMENT (continued)
TERMINAL
NAME
HFG
I/O
DESCRIPTION
This output can be programmed (SPI) to provide either the STATUS_REF or
PRI_SEC_CLK information. This pin is set high if one of the STATUS conditions is valid.
STATUS_REF is the default setting.
STATUS_REF or
PRI_SEC_CLK
50
O
In case of STATUS_REF, the LVCMOS output provides the Status of the Reference
Clock. If a reference clock with a frequency above 2 MHz is provided to PRI_REF or
SEC_REF STATUS_REF will be set high.
In case of PRI_SEC_CLK, the LVCMOS output indicates whether the primary clock
[high] or the secondary clock [low] is selected.
This LVCMOS output can be programmed (SPI) to provide either the STATUS_VCXO
information or serve as current path for the charge pump (CP). STATUS_VCXO is the
default setting.
STATUS_VCXO
or I_REF_CP
49
O
In case of STATUS_VCXO, the LVCMOS output provides the status of the VCXO input
(frequencies above 2 MHz are interpreted as valid clock; active high).
In case of I_REF_CP, it provides the current path for the external reference resistor
(12 kΩ ±1%) to support an accurate charge pump current, optional. Do not use any
capacitor across this resistor to prevent noise coupling via this node. If the internal 12 kΩ
is selected (default setting), this pin can be left open.
LVCMOS output for PLL_LOCK information. This pin is set high if the PLL is in lock (see
feature description). This output can be programmed to be digital lock detect or analog
lock detect (see feature description).
The PLL is locked (set high), if the rising edge either of PRI_REF or SEC_REF clock
and VCXO_IN clock at the phase frequency detector (PFD) are inside the lock detect
window for a predetermined number of successive clock cycles.
The PLL is out-of-lock (set low), if the rising edge of either the PRI_REF or SEC_REF)
clock and VCXO_IN clock at the PFD are outside the lock detect window or if a
cycle-slip occurs.
Both, the lock detect window and the number of successive clock cycles are user
definable (via SPI).
Y0A:Y0B
Y1A:Y1B
Y2A:Y2B
Y3A:Y3B
Y4A:Y4B
24, 25,
29, 30,
33, 34,
37,38,
42, 43
The outputs of the CDCM7005 are user definable and can be any combination of up to
five LVPECL outputs or up to 10 LVCMOS outputs. The outputs are selectable via SPI
(Word 1, Bit 2-6). The power-up setting is all outputs are LVPECL.
PLL_LOCK
52
I/O
O
ABSOLUTE MAXIMUM RATINGS
over operating free-air temperature range (unless otherwise noted)
(1)
UNIT
V
CC
, A
VCC
, V
CC_CP
V
I
V
O
I
OUT
I
IN
T
stg
T
J
(1)
(2)
(3)
Supply voltage range
Input voltage range
Output voltage range
(2)
–0.5 V to 4.6 V
–0.5 V to V
CC
+ 0.5 V
–0.5 V to V
CC
+ 0.5 V
±50 mA
±20 mA
–65°C to 150°C
125°C
(3)
(3)
Output current for LVPECL/LVCMOS outputs
(0 < V
O
< V
CC
)
Input current (V
I
< 0, V
I
> V
CC
)
Storage temperature range
Maximum junction temperature
Stresses beyond those listed under
absolute maximum ratings
may cause permanent damage to the device. These are stress ratings
only, and functional operation of the device at these or any other conditions beyond those indicated under
recommended operating
conditions
is not implied. Exposure to absolute–maximum–rated conditions for extended periods may affect device reliability.
All supply voltages have to be supplied at the same time.
The input and output negative voltage ratings may be exceeded if the input and output clamp-current ratings are observed.
Copyright © 2009, Texas Instruments Incorporated
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