WSF512K16-XXX
512K
X
16 SRAM / NOR FLASH MODULE (SMD 5962-96901*)
FEATURES
Access Times of 35ns (SRAM) and 90ns (FLASH)
Access Times of 70ns (SRAM) and 120ns (FLASH)
Packaging
• 66 pin, PGA Type, 1.385" square HIP, Hermetic Ceramic
HIP (Package 402)
• 68 lead, Hermetic CQFP (G2), 22mm (0.880") square
(Package 500). Designed to fit JEDEC 68 lead 0.990”
CQFJ footprint (FIGURE 2)
512Kx16 5V SRAM
512Kx16 5V NOR FLASH
Organized as 512Kx16 of SRAM and 512Kx16 of Flash
Memory with separate Data Busses
Both blocks of memory are User Configurable as 1Mx8
Low Power CMOS
Commercial, Industrial and Military Temperature Ranges
TTL Compatible Inputs and Outputs
Built-in Decoupling Caps and Multiple Ground Pins for Low
Noise Operation
Weight - 13 grams typical
FLASH MEMORY FEATURES
100,000 Erase/Program Cycles Minimum
Sector Architecture
• 8 equal size sectors of 64K bytes each
• Any combination of sectors can be concurrently erased.
Also supports full chip erase
5 Volt Programming
Embedded Erase and Program Algorithms
Hardware Write Protection
Page Program Operation and Internal Program Control
Time.
This product is subject to change without notice.
Note: For Flash programming information and waveforms refer to Flash Programming 4M5
Application Note AN0037.
* For reference only. See table page 10
FIGURE 1 – PIN CONFIGURATION
FOR WSF512K16-XH2X
TOP VIEW
1
SD8
SD9
SD10
A13
A14
A15
A16
A18
SD0
SD1
SD2
11
22
12
SWE2#
SCS2#
GND
SD11
A10
A11
A12
V
CC
SCS1#
NC
SD3
33
23
SD15
SD14
SD13
SD12
OE#
A17
SWE1#
SD7
SD6
SD5
SD4
FD8
FD9
FD10
A6
A7
NC
A8
A9
FD0
FD1
FD2
44
34
V
CC
FCS2#
FWE2#
FD11
A3
A4
A5
FWE1#
FCS1#
GND
FD3
55
45
FD15
FD14
FD13
FD12
A0
A1
A2
FD7
FD6
FD5
FD4
66
56
PIN DESCRIPTION
FD0-15
SD0-15
A0-18
SWE1-2#
SCS1-2#
OE#
V
CC
GND
NC
FWE1-2#
FCS1-2#
Flash Data Inputs/Outputs
SRAM Data Inputs/Outputs
Address Inputs
SRAM Write Enable
SRAM Chip Selects
Output Enable
Power Supply
Ground
Not Connected
Flash Write Enable
Flash Chip Select
BLOCK DIAGRAM
S W E 1 # S CS1# S W E 2 # S CS2# F W E 1 # F CS1# F W E 2 # F CS2#
OE#
A0-18
512K x 8
SRAM
512K x 8
SRAM
512K x 8
FLASH
512K x 8
FLASH
8
8
8
8
SD0-7
SD8-15
FD0-7
FD8-15
Microsemi Corporation reserves the right to change products or specifications without notice.
June 2012
Rev. 8
© 2012 Microsemi Corporation. All rights reserved.
1
Microsemi Corporation • (602) 437-1520 • www.microsemi.com
WSF512K16-XXX
FIGURE 2 – PIN CONFIGURATION
FOR WSF512K16-XG2X
TOP VIEW
PIN DESCRIPTION
FD0-15
SD0-15
A0-18
SWE1-2#
SCS1-2#
OE#
Flash Data Inputs/Outputs
SRAM Data Inputs/Outputs
Address Inputs
SRAM Write Enable
SRAM Chip Select
Output Enable
Power Supply
Ground
Not Connected
Flash Write Enable
Flash Chip Select
NC
A0
A1
A2
A3
A4
A5
FCS1#
GND
FCS2#
SWE1#
A6
A7
A8
A9
A10
V
CC
V
CC
GND
NC
FD0
FD1
FD2
FD3
FD4
FD5
FD6
FD7
GND
FD8
FD9
FD10
FD11
FD12
FD13
FD14
FD15
9 8 7 6 5 4 3 2 1 68 67 66 65 64 63 62 61
SD0
SD1
SD2
SD3
SD4
SD5
SD6
SD7
GND
SD8
SD9
SD10
SD11
SD12
SD13
SD14
SD15
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
60
59
58
57
56
55
54
53
52
51
50
49
48
47
46
45
44
27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43
FWE1-2#
FCS1-2#
BLOCK DIAGRAM
S W E 1 # S CS1# S W E 2 # S CS2# F W E 1 # F CS1# F W E 2 # F CS2#
OE#
A0-18
512K x 8
SRAM
512K x 8
SRAM
512K x 8
FLASH
512K x 8
FLASH
A17
SWE2#
FWE1#
FWE2#
A12
A13
A14
A15
A16
A18
A11
V
CC
SCS1#
OE#
SCS2#
NC
NC
8
8
8
8
SD0-7
SD8-15
FD0-7
FD8-15
The Microsemi 68 lead G2 CQFP
fi
lls the same
fi
t and function as
the JEDEC 68 lead CQFJ or 68 PLCC. But the G2 has the TCE and
lead inspection advantage of the CQFP form.
Microsemi Corporation reserves the right to change products or specifications without notice.
June 2012
Rev. 8
© 2012 Microsemi Corporation. All rights reserved.
2
Microsemi Corporation • (602) 437-1520 • www.microsemi.com
WSF512K16-XXX
ABSOLUTE MAXIMUM RATINGS
Parameter
Operating Temperature (Mil, Q)
Storage Temperature
Signal Voltage Relative to GND
Supply Voltage
Symbol
T
A
T
STG
V
G
V
CC
Min
-55
-65
-0.5
-0.5
Max
+125
+150
7.0
7.0
Unit
°C
°C
V
V
SCS#
H
L
L
L
OE#
X
L
H
X
SRAM TRUTH TABLE
SWE#
X
H
H
L
Mode
Standby
Read
Read
Write
Data I/O
High Z
Data Out
High Z
Data In
Power
Standby
Active
Active
Active
NOTE: Auto select mode that require high voltage (V
ID
) is not available. Flash and SRAM
share same address bus and would damage SRAM inputs.
Parameter
Flash Data Retention
Flash Endurance (write/erase cycles)
20 years
100,000 min.
Test
OE# Capacitance
F/S WE1-2# Capacitance
F/S CS1-2# Capacitance
Data I/O Capacitance
Address Input Capacitance
CAPACITANCE
T
A
= +25°C
Symbol
C
OE
C
WE
C
CS
C
I/O
C
AD
Condition
V
IN
= 0V, f = 1.0MHz
V
IN
= 0V, f = 1.0MHz
V
IN
= 0V, f = 1.0MHz
V
IN
= 0V, f = 1.0MHz
V
IN
= 0V, f = 1.0MHz
Max
50
20
20
20
50
Unit
pF
pF
pF
pF
pF
NOTES: 1. Stresses above the absolute maximum rating may cause permanent damage to the
device. Extended operation at the maximum levels may degrade performance and
affect reliability.
RECOMMENDED OPERATING CONDITIONS
Parameter
Supply Voltage
Input High Voltage
Input Low Voltage
Operating Temp. (Mil., Q)
Operating Temp. (Ind.)
Operating Temp. (Com.)
Symbol
V
CC
V
IH
V
IL
T
A
T
A
T
A
Min
4.5
2.2
-0.5
-55
-40
0
Max
5.5
V
CC
+ 0.3
+0.8
+125
+85
+70
Unit
V
V
V
°C
°C
°C
This parameter is guaranteed by design but not tested.
DC CHARACTERISTICS – CMOS COMPATIBLE
Parameter
Input Leakage Current
Output Leakage Current
SRAM Operating Supply Current x 16 Mode
Standby Current
SRAM Output Low Voltage
SRAM Output High Voltage
Flash V
CC
Active Current for Read (1, 2)
Flash V
CC
Active Current for Program or Erase (2, 3)
Flash Output Low Voltage
Flash Output High Voltage
Flash Low V
CC
Lock Out Voltage
Symbol
I
LI
I
LO
I
CCx16
I
SB
V
OL
V
OH
I
CC1
I
CC2
V
OL
V
OH1
V
LKO
Conditions
V
CC
= 5.5, V
IN
= GND to V
CC
FCS# = SCS# = V
IH
, OE# = V
IH
, V
OUT
= GND to V
CC
SCS# = V
IL
, OE# = FCS# = V
IH
, f = 5MHz, V
CC
= V
CC MAX
FCS# = SCS# = V
CC
± 0.5V, OE# = V
IH
, f = 5MHz, V
CC
= V
CC MAX
I
OL
= 6mA, V
CC
= V
CC MIN
I
OH
= -1.0mA, V
CC
= V
CC MIN
FCS# = V
IL
, OE# = SCS# = V
IH
FCS# = V
IL
, OE# = SCS# = V
IH
I
OL
= 12mA, V
CC
= V
CC MIN
I
OH
= -2.5 mA, V
CC
= V
CC MIN
Min
Max
10
10
270
45
0.4
130
150
0.45
0.85 x V
CC
3.2
4.2
Unit
μA
μA
mA
mA
V
V
mA
mA
V
V
V
2.4
NOTES:
1. The I
CC
current listed includes both the DC operating current and the frequency dependent component (@ 5 MHz).
The frequency component typically is less than 4mA/MHz, with OE# at V
IH
.
2. Maximum current specification are tested with V
CC
= V
CC MAX
3. I
CC
active while Embedded Algorithm (program or erase) is in progress.
Microsemi Corporation reserves the right to change products or specifications without notice.
June 2012
Rev. 8
© 2012 Microsemi Corporation. All rights reserved.
3
Microsemi Corporation • (602) 437-1520 • www.microsemi.com
WSF512K16-XXX
SRAM AC CHARACTERISTICS
Parameter
Read Cycle
Read Cycle Time
Address Access Time
Output Hold from Address Change
Chip Select Access Time
Output Enable to Output Valid
Chip Select to Output in Low Z (1)
Output Enable to Output in Low Z (1)
Chip Disable to Output in High Z (1)
Output Disable to Output in High Z (1)
Symbol
t
RC
t
AA
t
OH
t
ACS
t
OE
t
CLZ
t
OLZ
t
CHZ
t
OHZ
-35
35
35
0
35
25
4
0
15
15
10
5
25
25
5
70
35
70
70
-70
Min Max Min Max
Unit
ns
ns
ns
ns
ns
ns
ns
ns
ns
Parameter
SRAM AC CHARACTERISTICS
Write Cycle
Write Cycle Time
Chip Select to End of Write
Address Valid to End of Write
Data Valid to End of Write
Write Pulse Width
Address Setup Time
Address Hold Time
Output Active from End of Write (1)
Write Enable to Output in High Z (1)
Data Hold from Write Time
Symbol
t
WC
t
CW
t
AW
t
DW
t
WP
t
AS
t
AH
t
OW
t
WHZ
t
DH
-35
35
25
25
20
25
0
0
0
15
0
0
70
60
60
30
50
0
5
5
25
-70
Min Max Min Max
Unit
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
1. This parameter is guaranteed by design but not tested.
1. This parameter is guaranteed by design but not tested.
FIGURE 3 – AC TEST CIRCUIT
Parameter
Input Pulse Levels
Input Rise and Fall
AC TEST CONDITIONS
Typ
V
IL
= 0, V
IH
= 3.0
5
1.5
1.5
Unit
V
ns
V
V
I
OL
Current Source
Input and Output Reference Level
Output Timing Reference Level
D.U.T.
C
eff
= 50 pf
VZ ≈ 1.5V
(Bipolar Supply)
Notes: V
Z
is programmable from -2V to +7V.
I
OL
& I
OH
programmable from 0 to 16mA.
Tester Impedance Z0 = 75Ω.
V
Z
is typically the midpoint of V
OH
and V
OL
.
I
OL
& I
OH
are adjusted to simulate a typical resistive load circuit.
ATE tester includes jig capacitance.
I
OH
Current Source
Microsemi Corporation reserves the right to change products or specifications without notice.
June 2012
Rev. 8
© 2012 Microsemi Corporation. All rights reserved.
4
Microsemi Corporation • (602) 437-1520 • www.microsemi.com
WSF512K16-XXX
FIGURE 4 – SRAM TIMING WAVEFORM — READ CYCLE
t
RC
ADDRESS
t
RC
ADDRESS
t
AA
SCS#
t
AA
t
OH
DATA I/O
PREVIOUS DATA VALID
DATA VALID
t
ACS
t
CLZ
SOE#
t
CHZ
READ CYCLE 1 (SCS# = OE# = V
IL
, SWE# = V
IH
)
t
OE
t
OLZ
DATA I/O
HIGH IMPEDANCE
t
OHZ
DATA VALID
READ CYCLE 2 (SWE# = V
IH
)
FIGURE 5 – SRAM WRITE CYCLE — SWE# CONTROLLED
t
WC
ADDRESS
t
AW
SCS#
t
CW
t
AH
t
AS
SWE#
t
WP
t
OW
t
WHZ
t
DW
DATA VALID
t
DH
DATA I/O
WRITE CYCLE 1, SWE# CONTROLLED
FIGURE 6 – SRAM WRITE CYCLE — SCS# CONTROLLED
t
WC
ADDRESS
t
AS
SCS#
t
AW
t
CW
t
WP
t
AH
SWE#
t
DW
DATA I/O
DATA VALID
t
DH
WRITE CYCLE 2, SCS# CONTROLLED
Microsemi Corporation reserves the right to change products or specifications without notice.
June 2012
Rev. 8
© 2012 Microsemi Corporation. All rights reserved.
5
Microsemi Corporation • (602) 437-1520 • www.microsemi.com
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