DATA SHEET
Integrated
LOW SKEW, 1-TO-4 CRYSTAL
Circuit
Systems, Inc.
OSCILLATOR/DIFFERENTIAL-TO-3.3V
L
OW
S
KEW
, 1-
TO
-4, C
RYSTAL
O
SCILLATOR
/
LVPECL FANOUT
D
IFFERENTIAL
-
TO
-3.3V LVPECL F
ANOUT
B
UFFER
F
EATURES
•
4 differential 3.3V LVPECL outputs
•
Selectable differential CLK, nCLK or crystal inputs
•
CLK, nCLK pair can accept the following differential
input levels: LVPECL, LVDS, LVHSTL, SSTL, HCSL
•
Maximum output frequency: 650MHz
•
Translates any single-ended input signal to 3.3V
LVPECL levels with resistor bias on nCLK input
•
Output skew: 30ps (maximum)
•
Part-to-part skew: 150ps (maximum)
•
Propagation delay: 2ns (maximum)
•
3.3V operating supply
•
0°C to 70°C ambient operating temperature
•
Industrial temperature information available upon request
•
Lead-Free package fully RoHS compliant
ICS8533-11
ICS8533-11
G
ENERAL
D
ESCRIPTION
The ICS8533-11 is a low skew, high performance
1-to-4 Crystal Oscillator/Differential-to-3.3V
HiPerClockS™
LVPECL fanout buffer and a member of the
HiPerClockS™family of High Performance Clock
Solutions from ICS. The ICS8533-11 has select-
able differential clock or crystal inputs. The CLK, nCLK pair
can accept most standard differential input levels. The clock
enable is internally synchronized to eliminate runt pulses on
the outputs during asynchronous assertion/deassertion of the
clock enable pin.
ICS
Guaranteed output and part-to-part skew characteristics
make the ICS8533-11 ideal for those applications demand-
ing well defined performance and repeatability.
B
LOCK
D
IAGRAM
CLK_EN
D
Q
LE
CLK
nCLK
XTAL1
XTAL2
0
1
Q0
nQ0
Q1
nQ1
CLK_SEL
Q2
nQ2
Q3
nQ3
P
IN
A
SSIGNMENT
V
EE
CLK_EN
CLK_SEL
CLK
nCLK
XTAL1
XTAL2
nc
nc
V
CC
1
2
3
4
5
6
7
8
9
10
20
19
18
17
16
15
14
13
12
11
Q0
nQ0
V
CC
Q1
nQ1
Q2
nQ2
V
CC
Q3
nQ3
ICS8533-11
20-Lead TSSOP
6.5mm x 4.4mm x 0.92 package body
G Package
Top View
8533AG-11
www.icst.com/products/hiperclocks.html
REV. E DECEMBER 14, 2004
IDT™ / ICS™
LOW SKEW, 1-TO-4 CRYSTAL OSCILLATOR/DIFFERENTIAL-TO-3.3V LVPECL FANOUT BUFFER
1
1
ICS8533-11
ICS8533-11
Circuit
OW KEW
TO
RYSTAL
LOW SKEW, 1-TO-4 CRYSTAL OSCILLATOR/DIFFERENTIAL-TO-3.3V LVPECL FANOUT BUFFER
Integrated
ICS8533-11
Systems, Inc.
S , 1- -4, C
O
SCILLATOR
/
TSD
D
IFFERENTIAL
-
TO
-3.3V LVPECL F
ANOUT
B
UFFER
L
T
ABLE
1. P
IN
D
ESCRIPTIONS
Number
1
2
3
4
5
6
7
8, 9
10, 13, 18
11, 12
14, 15
16, 17
19, 20
Name
V
EE
CLK_EN
CLK_SEL
CLK
nCLK
XTAL1
XTAL2
nc
V
CC
nQ3, Q3
nQ2, Q2
nQ1, Q1
nQ0, Q0
Power
Input
Input
Input
Input
Input
Input
Unused
Power
Output
Output
Output
Output
Type
Description
Negative supply pin.
Synchronizing clock enable. When HIGH, clock outputs follows clock input.
When LOW, Q outputs are forced low, nQ outputs are forced high.
Pullup
LVCMOS / LVTTL interface levels.
Clock select input. When LOW, selects CLK, nCLK input.
Pulldown
When HIGH, selects XTAL input. LVCMOS / LVTTL interface levels.
Pulldown Non-inver ting differential clock input.
Pullup
Pullup
Inver ting differential clock input.
Cr ystal oscillator input.
No connect.
Positive supply pins.
Differential clock outputs. LVPECL interface levels.
Differential clock outputs. LVPECL interface levels.
Differential clock outputs. LVPECL interface levels.
Differential clock outputs. LVPECL interface levels.
Pulldown Cr ystal oscillator input.
NOTE:
Pullup
and
Pulldown
refer to internal input resistors. See Table 2, Pin characteristics, for typical values.
T
ABLE
2. P
IN
C
HARACTERISTICS
Symbol
C
IN
R
PULLUP
R
PULLDOWN
Parameter
Input Capacitance
Input Pullup Resistor
Input Pulldown Resistor
Test Conditions
Minimum
Typical
4
51
51
Maximum
Units
pF
KΩ
KΩ
8533AG-11
www.icst.com/products/hiperclocks.html
2
REV. E DECEMBER 14, 2004
IDT™ / ICS™
LOW SKEW, 1-TO-4 CRYSTAL OSCILLATOR/DIFFERENTIAL-TO-3.3V LVPECL FANOUT BUFFER
2
ICS8533-11
ICS8533-11
Circuit
OW KEW
TO
RYSTAL
LOW SKEW, 1-TO-4 CRYSTAL OSCILLATOR/DIFFERENTIAL-TO-3.3V LVPECL FANOUT BUFFER
Integrated
ICS8533-11
Systems, Inc.
S , 1- -4, C
O
SCILLATOR
/
TSD
D
IFFERENTIAL
-
TO
-3.3V LVPECL F
ANOUT
B
UFFER
Outputs
L
T
ABLE
3A. C
ONTROL
I
NPUT
F
UNCTION
T
ABLE
Inputs
CLK_EN
0
0
1
CLK_SEL
0
1
0
Selected Source
CLK, nCLK
XTAL1, XTAL2
CLK, nCLK
Q0:Q3
Disabled; LOW
Disabled; LOW
Enabled
nQ0:nQ3
Disabled; HIGH
Disabled; HIGH
Enabled
1
1
XTAL1, XTAL2
Enabled
Enabled
After CLK_EN switches, the clock outputs are disabled or enabled folowing a rising and falling input clock or
crystal oscillator edge as shown in
Figure 1
.
In the active mode, the state of the outputs are a function of the CLK, nCLK and XTAL1, XTAL2 inputs as described
in Table 3B.
nCLK
CLK
Disabled
Enabled
CLK_EN
nQ0:nQ3
Q0:Q3
F
IGURE
1. CLK_EN T
IMING
D
IAGRAM
T
ABLE
3B. C
LOCK
I
NPUT
F
UNCTION
T
ABLE
Inputs
CLK
0
1
0
1
Biased; NOTE 1
Biased; NOTE 1
nCLK
1
0
Biased; NOTE 1
Biased; NOTE 1
0
1
Q0:Q3
LOW
HIGH
LOW
HIGH
HIGH
LOW
Outputs
nQ0:nQ3
HIGH
LOW
HIGH
LOW
LOW
HIGH
Input to Output Mode
Differential to Differential
Differential to Differential
Single Ended to Differential
Single Ended to Differential
Single Ended to Differential
Single Ended to Differential
Polarity
Non Inver ting
Non Inver ting
Non Inver ting
Non Inver ting
Inver ting
Inver ting
NOTE 1: Please refer to the Application Information section, "Wiring the Differential Input to Accept Single Ended Levels".
8533AG-11
www.icst.com/products/hiperclocks.html
3
REV. E DECEMBER 14, 2004
IDT™ / ICS™
LOW SKEW, 1-TO-4 CRYSTAL OSCILLATOR/DIFFERENTIAL-TO-3.3V LVPECL FANOUT BUFFER
3
ICS8533-11
ICS8533-11
Circuit
OW KEW
TO
RYSTAL
LOW SKEW, 1-TO-4 CRYSTAL OSCILLATOR/DIFFERENTIAL-TO-3.3V LVPECL FANOUT BUFFER
Integrated
ICS8533-11
Systems, Inc.
S , 1- -4, C
O
SCILLATOR
/
TSD
D
IFFERENTIAL
-
TO
-3.3V LVPECL F
ANOUT
B
UFFER
L
A
BSOLUTE
M
AXIMUM
R
ATINGS
Supply Voltage, V
CC
Inputs, V
I
Outputs, I
O
Continuous Current
Surge Current
Package Thermal Impedance,
θ
JA
Storage Temperature, T
STG
4.6V
-0.5V to V
CC
+ 0.5V
50mA
100mA
73.2°C/W (0 lfpm)
-65°C to 150°C
NOTE: Stresses beyond those listed under Absolute
Maximum Ratings may cause permanent damage to the
device. These ratings are stress specifications only. Functional
operation of product at these conditions or any conditions be-
yond those listed in the
DC Characteristics
or
AC Character-
istics
is not implied. Exposure to absolute maximum rating
conditions for extended periods may affect product reliability.
T
ABLE
4A. P
OWER
S
UPPLY
DC C
HARACTERISTICS
,
V
CC
= 3.3V±5%, T
A
= 0°C
TO
70°C
Symbol
V
CC
I
EE
Parameter
Power Supply Voltage
Power Supply Current
Test Conditions
Minimum
3.135
Typical
3.3
Maximum
3.465
50
Units
V
mA
T
ABLE
4B. LVCMOS / LVTTL DC C
HARACTERISTICS
,
V
CC
= 3.3V±5%, T
A
= 0°C
TO
70°C
Symbol
V
IH
V
IL
I
IH
I
IL
Parameter
Input High Voltage
Input Low Voltage
Input High Current
Input Low Current
CLK_EN,
CLK_SEL
CLK_EN,
CLK_SEL
CLK_EN
CLK_SEL
CLK_EN
CLK_SEL
Test Conditions
Minimum
2
-0.3
V
IN
= V
CC
= 3.465V
V
IN
= V
CC
= 3.465V
V
IN
= 0V, V
CC
= 3.465V
V
IN
= 0V, V
CC
= 3.465V
-150
-5
Typical
Maximum
V
CC
+ 0.3
0.8
5
150
Units
V
V
µA
µA
µA
µA
T
ABLE
4C. D
IFFERENTIAL
DC C
HARACTERISTICS
,
V
CC
= 3.3V±5%, T
A
= 0°C
TO
70°C
Symbol
I
IH
I
IL
V
PP
Parameter
Input High Current
Input Low Current
nCLK
CLK
nCLK
CLK
Test Conditions
V
CC
= V
IN
= 3.465V
V
CC
= V
IN
= 3.465V
V
CC
= 3.465V, V
IN
= 0V
V
CC
= 3.465V, V
IN
= 0V
-150
-5
1.3
V
CC
- 0.85
Minimum Typical
Maximum
5
150
Units
µA
µA
µA
µA
V
V
Peak-to-Peak Input Voltage
0.15
Common Mode Input Voltage;
V
CMR
V
EE
+ 0.5
NOTE 1, 2
NOTE1: For single ended applications the maximum input voltage for CLK and nCLK is V
CC
+ 0.3V.
NOTE 2: Common mode voltage is defined as V
IH
.
8533AG-11
www.icst.com/products/hiperclocks.html
4
REV. E DECEMBER 14, 2004
IDT™ / ICS™
LOW SKEW, 1-TO-4 CRYSTAL OSCILLATOR/DIFFERENTIAL-TO-3.3V LVPECL FANOUT BUFFER
4
ICS8533-11
ICS8533-11
Circuit
OW KEW
TO
RYSTAL
LOW SKEW, 1-TO-4 CRYSTAL OSCILLATOR/DIFFERENTIAL-TO-3.3V LVPECL FANOUT BUFFER
Integrated
ICS8533-11
Systems, Inc.
S , 1- -4, C
O
SCILLATOR
/
TSD
D
IFFERENTIAL
-
TO
-3.3V LVPECL F
ANOUT
B
UFFER
Minimum
V
CC
- 1.4
V
CC
- 2.0
0. 6
Typical
Maximum
V
CC
- 1.0
V
CC
- 1.7
1.0
Units
V
V
V
L
T
ABLE
4D. LVPECL DC C
HARACTERISTICS
,
V
CC
= 3.3V±5%, T
A
= 0°C
TO
70°C
Symbol
V
OH
V
OL
V
SWING
Parameter
Output High Voltage; NOTE 1
Output Low Voltage; NOTE 1
Peak-to-Peak Output Voltage Swing
Test Conditions
NOTE 1: Outputs terminated with 50
Ω
to V
CC
- 2V.
T
ABLE
5. C
RYSTAL
C
HARACTERISTICS
Parameter
Mode of Oscillation
Frequency
Equivalent Series Resistance (ESR)
Shunt Capacitance
14
Test Conditions
Minimum Typical
Maximum
25
50
7
Units
MHz
Ω
pF
Fundamental
T
ABLE
6. AC C
HARACTERISTICS
,
V
CC
= 3.3V±5%, T
A
= 0°C
TO
70°C
Symbol Parameter
f
MAX
t
PD
Output Frequency
Propagation Delay; NOTE 1
Output Skew; NOTE 2, 5
Par t-to-Par t Skew; NOTE 3, 5
Output Rise/Fall Time
20% to 80% @ 50MHz
300
IJ 650MHz
1.0
Test Conditions
Minimum
Typical
Maximum
650
2.0
30
150
700
53
Units
MHz
ns
ps
ps
ps
%
t
sk(o)
t
sk(pp)
t
R
/ t
F
odc
Output Duty Cycle; NOTE 4
47
50
All parameters measured at 500MHz unless noted otherwise.
The cycle-to-cycle jitter on the input will equal the jitter on the output. The par t does not add jitter.
NOTE 1: Measured from the differential input crossing point to the differential output crossing point.
NOTE 2: Defined as skew between outputs at the same supply voltage and with equal load conditions.
Measured at the output differential cross points.
NOTE 3: Defined as skew between outputs on different devices operating at the same supply voltages
and with equal load conditions. Using the same type of inputs on each device, the outputs are measured
at the differential cross points.
NOTE 4: Measured using CLK. For XTAL input, refer to Application Note.
NOTE 5: This parameter is defined in accordance with JEDEC Standard 65.
8533AG-11
www.icst.com/products/hiperclocks.html
5
REV. E DECEMBER 14, 2004
IDT™ / ICS™
LOW SKEW, 1-TO-4 CRYSTAL OSCILLATOR/DIFFERENTIAL-TO-3.3V LVPECL FANOUT BUFFER
5
ICS8533-11
京公网安备 11010802033920号
Copyright © 2005-2026 EEWORLD.com.cn, Inc. All rights reserved
电子工程世界
