INT201
High-side Driver IC
Floating Inputs
Floating High-side Drive
Product Highlights
Floating Control Inputs
• Connects directly to INT200 or INT202 HSD outputs
• No external level translators or transformers required
Gate Drive Output for an External MOSFET
• Provides 300 mA sink/150 mA source current
• Can drive MOSFET gate at up to 15 V
• Floating source for driving high-side N-channel MOSFET
• External MOSFET allows flexibility in design for various
motor sizes
VDD
®
HV
INT201
Built-in Protection Circuits
• Logic inputs include noise rejection circuitry
• Undervoltage lockout
HS IN
INT200
LS IN
3-PHASE
BRUSHLESS
DC MOTOR
PI-1764-020196
Figure 1. Typical Application.
Description
The INT201 high-side driver IC provides gate drive for an
external high-side MOSFET switch. When used in conjunction
with the INT200 or INT202 low-side drivers, the INT201
provides a simple, cost-effective interface between low-voltage
control logic and high-voltage loads.
Built-in noise rejection circuitry shared between the INT201
and the INT200 or INT202 provides reliable operation in the
harshest industrial environments. The INT201 is powered from
a ground-referenced low-voltage supply. A floating supply is
derived from this rail by using a simple bootstrap technique to
provide adequate gate drive for the external N-channel MOSFET.
Applications include motor drives, electronic ballasts, and
uninterruptible power supplies. The INT201 can also be used
to implement full-bridge and multi-phase configurations.
The INT201 is available in 8-pin plastic DIP and SOIC packages.
N/C
1
N/C
2
HSD1
3
HSD2
4
8
7
6
5
VDDH
N/C
HS OUT
SOURCE
PI–285D–091191
Figure 2. Pin Configuration.
ORDERING INFORMATION
PART
NUMBER
INT201PFI
INT201TFI
PACKAGE
OUTLINE
P08A
T08A
TEMP
RANGE
-40 to 85°C
-40 to 85°C
February 1996
INT201
Pin Functional Description
Pin 1:
No connection.
Pin 2:
No connection.
Pin 3:
Level shift input
HSD 1
works in
conjunction with HSD 2 to provide
interface from the low side control logic
and to give noise immunity.
Pin 4:
Level shift input
HSD 2
works in
conjunction with HSD 1 to provide
interface from the low side control logic
and to give noise immunity.
Pin 5:
SOURCE
connection. Analog reference
point for the circuit, normally connected
to the source of the high side MOSFET.
Pin 6:
HS OUT
is the output of the MOSFET
driver for the high side.
Pin 7:
No connection.
Pin 8:
V
DDH
supplies power to the control logic
and output driver.
VDDH
LINEAR
REGULATOR
HSD1
DISCRIMINATOR
UV
LOCKOUT
S
R
Q
DELAY
HS OUT
HSD2
SOURCE
PI-514B-021792
Figure 3. Functional Block Diagram of the INT201.
INT201 Functional Description
5 V Regulator
The 5 V linear regulator circuit provides
the supply voltage for the noise rejection
circuitry and control logic. This allows
the logic section and the driver circuitry
to be directly compatible with 5 V CMOS
logic without the need of an external 5 V
supply.
Undervoltage Lockout
The undervoltage lockout circuit disables
the HS OUT pin whenever the V
DDH
power supply falls below 9.0 V, and
maintains this condition until the V
DDH
power supply rises above 9.35 V. This
guarantees that the high side MOSFET
will be off during power-up or fault
conditions.
Noise Immunization Circuit
This circuit provides noise immunity by
combining a sampling circuit with a
flip-flop to turn on and off the driver
only when required to and not when
there is noise on the HSD inputs.
Driver
The CMOS driver circuit provides drive
power to the gate of the MOSFET used
on the high side of the half bridge circuit.
The driver consists of a CMOS buffer
capable of driving external transistors at
up to 15 V. The SOURCE pin is
connected to the source of the external
MOSFET to establish a reference for the
gate voltage.
2
F
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INT201
HV+
8
7
6
5
R2
C2
D1
1
Q2
PHASE 2
INT201
2
3
4
VDD
8
7
6
5
PHASE 1
C1
INT200
1
2
3
4
Q1
PHASE 3
3-PHASE
BRUSHLESS
DC MOTOR
HS IN
LS IN
HV-
R1
PI-1467-042695
Figure 4. Using the INT200 and INT201 in a 3-phase Configuration.
General Circuit Operation
One phase of a three-phase brushless
DC motor drive circuit is shown in Figure
4 to illustrate an application of the
INT200/201. The LS IN signal directly
controls MOSFET Q1. The
HS IN
signal
causes the INT200 to command the
INT201 to turn MOSFET Q2 on or off as
required. The INT200 will ignore input
signals that would command both Q1
and Q2 to conduct simultaneously,
protecting against shorting the HV+ bus
to HV-.
Local bypassing for the low-side driver
is provided by C1. Bootstrap bias for the
high-side driver is provided by D1 and
C2. Slew rate and effects of parasitic
oscillations in the load waveforms are
controlled by resistors R1 and R2.
The inputs are designed to be compatible
with 5 V CMOS logic levels and should
not be connected to V
DD
. Normal CMOS
power supply sequencing should be
observed. The order of signal application
should be V
DD
, logic signals, and then
HV+.
The INT201 is latched on and off by the
edges of the appropriate low-side logic
signal (
HS IN
for the INT200 and
HS IN
for the INT202). The high-side driver
will latch off and stay off if the bootstrap
capacitor discharges below the
1000
Bootstrap Capacitance (µF)
undervoltage lockout threshold.
Undervoltage lockout-induced turn off
can occur during conditions such as
power ramp up, motor start, or low speed
operation.
C
BOOTSTRAP
vs. ON TIME
PI-566B-030692
100
10
QG = 100 nC
1
0.1
QG = 20 nC
0.01
0.01
0.1
1
10
100
High Side ON Time (ms)
Figure 5. High-side On Time versus Bootstrap Capacitor.
F
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3
INT201
HV+
8
7
6
5
R2
C2
D1
1
D3
PHASE 2
Q2
INT201
2
3
4
VDD
8
7
6
5
3-PHASE
SRM
PHASE 1
C1
INT202
1
2
3
4
PHASE 3
R1
Q1
D2
CONTROL
HV-
PI-1468-042695
Figure 6. Using the INT202 and INT201 to Drive a Switched Reluctance Motor.
General Circuit Operation (cont.)
The bootstrap capacitor must be large
enough to provide bias current over the
entire on time interval of the high-side
driver without significant voltage sag or
decay. The MOSFET gate charge must
also be supplied at the desired switching
frequency. Figure 5 shows the maximum
high-side on time versus gate charge of
the external MOSFET. Applications
with extremely long high-side on times
require special techniques discussed in
AN-10.
A three-phase switched reluctance motor
example using the INT202/201 is given
in Figure 6. The LS IN signal directly
controls MOSFET Q1. Unlike the
INT200, the INT202 allows both the
low and high-side drivers to be on at the
same time, as this is required in
applications where the load is placed
between the low and high-side output
MOSFETs.
4
F
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INT201
ABSOLUTE MAXIMUM RATINGS
1
V
DDH
Voltage ............................................................ 16.5 V
Logic Input Voltage ................................... -0.3 V to 5.5 V
HS OUT Voltage ............................ -0.3 V to V
DDH
+ 0.3 V
Storage Temperature ..................................... –65 to 125°C
Ambient Temperature ...................................... -40 to 85°C
Junction Temperature. .............................................. 150°C
Lead Temperature
(2)
. ................................................ 260°C
Power Dissipation
PF Suffix (T
A
= 25˚C) .......................................... 1.25 W
PF Suffix (T
A
= 70˚C) ........................................ 800 mW
TF Suffix (T
A
= 25˚C) .......................................... 1.04 W
TF Suffix (T
A
= 70˚C) ........................................ 667 mW
Thermal Impedance (θ
JA
)
PF Suffix ............................................................. 100°C/W
TF Suffix ............................................................. 120°C/W
1. Unless noted, all voltages referenced to SOURCE,
T
A
= 25˚C
2. 1/16" from case for 5 seconds.
Conditions
Parameter
Symbol
(Unless Otherwise Specified)
V
DDH
= 15 V, SOURCE = 0V
T
A
= -40 to 85°C
Min
Typ
Max
Units
HSD INPUTS
Input Current
Threshold
HS OUT
Output Voltage,
High
Output Voltage,
Low
Output Short
Circuit Current
Turn-on
Delay Time
Rise
Time
Turn-off
Delay Time
Fall
Time
V
OH
V
OL
I
OS
t
d(on)
t
r
t
d(off)
t
f
I
o
= -20 mA
I
o
= 40 mA
V
O
= 0 V
V
O
= V
DDH
300
1.0
1.5
V
DDH
-1.0 V
DDH
-0.5
0.3
1.0
-150
mA
µs
V
I
HSD1
, I
HSD2
-5
-2.5
mA
V
See Note 1
See Figure 7
See Figure 7
80
120
ns
See Figure 7
420
600
ns
See Figure 7
50
100
ns
F
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5
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