PRELIMINARY
Integrated
Circuit
Systems, Inc.
ICS844008I-15
F
EMTO
C
LOCKS
™ C
RYSTAL
-
TO
-
LVDS F
REQUENCY
S
YNTHESIZER
F
EATURES
• Eight LVDS outputs
• Crystal oscillator interface
• Supports the following output frequencies:
100MHz or 125MHz
• VCO: 500MHz
• RMS phase jitter @ 125MHz, using a 25MHz crystal
(1.875MHz - 20MHz): 0.42ps (typical)
• Full 3.3V supply modes
• -40°C to 85°C ambient operating temperature
• Available in both standard and lead-free RoHS compliant
packages
G
ENERAL
D
ESCRIPTION
The ICS844008I-15 is an 8 output LVDS
Synthesizer optimized to generate PCI Express
HiPerClockS™
reference clock frequencies and is a member
of the HiPerClocks
TM
family of high performance
clock solutions from ICS. Using a 25MHz
parallel resonant crystal, the following frequencies can be
generated based on F_SEL pin: 100MHz or 125MHz. The
ICS844008I-15 uses ICS’ 3
rd
generation low phase noise
VCO technology and can achieve <1ps typical rms phase
jitter, easily meeting PCI Express jitter requirements. The
ICS844008I-15 is packaged in a 32-pin LQFP package.
IC
S
F
REQUENCY
S
ELECT
F
UNCTION
T
ABLE
Input
Input
Frequency
(MHz)
25MHz
25MHz
M Divider
Value
20
20
N Divider
Value
4
5
M/N Divider
Value
5
4
Output
Frequency
(MHz)
12 5
100
F_SEL
0
1
B
LOCK
D
IAGRAM
OE1
Pullup
Q0
nPLL_SEL
Pulldown
P
IN
A
SSIGNMENT
XTAL_OUT
nPLL_SEL
XTAL_IN
V
DDA
GND
OE1
OE2
V
DD
nQ0
Q1
1
nQ1
Q2
0
÷4
÷5
nQ2
Q3
nQ3
Q0
nQ0
1
2
3
4
5
6
7
8
9 10 11 12 13 14 15 16
F_SEL
Q3
nQ3
V
DD
GND
Q4
nQ4
MR
32 31 30 29 28 27 26 25
24
Q7
nQ7
V
DD
Q6
nQ6
GND
Q5
nQ5
XTAL_IN
25MHz
OSC
XTAL_OUT
Phase
Detector
VCO
500MHz
(w/25MHz
Reference)
V
DD
Q1
nQ1
GND
Q2
nQ2
ICS844008I-15
32-Lead LQFP
7mm x 7mm x 1.4mm
package body
Y Package
Top View
23
22
21
20
19
18
17
M =
÷
20 (fixed)
Q4
nQ4
Q5
nQ5
Q6
nQ6
Q7
MR
Pulldown
F_SEL
OE2
Pullup
Pullup
nQ7
The Preliminary Information presented herein represents a product in prototyping or pre-production. The noted characteristics are based on
initial product characterization. Integrated Circuit Systems, Incorporated (ICS) reserves the right to change any circuitry or specifications
without notice.
844008AYI-15
www.icst.com/products/hiperclocks.html
REV. B APRIL 28, 2006
1
PRELIMINARY
Integrated
Circuit
Systems, Inc.
ICS844008I-15
F
EMTO
C
LOCKS
™ C
RYSTAL
-
TO
-
LVDS F
REQUENCY
S
YNTHESIZER
Type
Description
Differential output pair. LVDS interface levels.
Core supply pin.
Differential output pair. LVDS interface levels.
Power supply ground.
Differential output pair. LVDS interface levels.
Pullup
Frequency select pin LVCMOS/LVTTL interface levels.
Differential output pair. LVDS interface levels.
Differential output pair. LVDS interface levels.
Active HIGH Master Reset. When logic HIGH, the internal dividers are reset
causing the true outputs Qx to go low and the inver ted outputs nQx
to go high. When logic LOW, the internal dividers and the outputs are
enabled. LVCMOS/LVTTL interface levels.
Differential output pair. LVDS interface levels.
Differential output pair. LVDS interface levels.
Differential output pair. LVDS interface levels.
T
ABLE
1. P
IN
D
ESCRIPTIONS
Number
1, 2
3, 12,
22, 27
4, 5
6, 13,
19, 29
7, 8
9
10, 11
14, 15
16
17, 18
20, 21
23, 24
25
Name
Q0, nQ0
V
DD
Q1, nQ1
GND
Q2, nQ2
F_SEL
Q3, nQ3
Q4, nQ4
MR
nQ5, Q5
nQ6, Q6
nQ7, Q7
V
DDA
Output
Power
Ouput
Power
Output
Input
Output
Output
Input
Output
Output
Output
Power
Pulld-
own
Analog supply pin.
Selects between the PLL and REF_CLK as input to the dividers. When LOW,
Pulld-
selects PLL (PLL Enable). When HIGH, deselects the reference clock (PLL
26
nPLL_SEL
Input
own
Bypass). LVCMOS/LVTTL interface levels.
Output enable for Q5/nQ5:Q7/nQ7 outputs.
28
OE2
Input
Pullup
LVCMOS/LVTTL interface levels.
Parallel resonant cr ystal interface. XTAL_OUT is the output,
XTAL_OUT,
30, 31
Input
XTAL_IN is the input.
XTAL_IN
Output enable for Q0/nQ0:Q4/nQ4 outputs.
32
OE1
Input
Pullup
LVCMOS/LVTTL interface levels.
NOTE:
Pullup
refers to internal input resistors. See Table 2, Pin Characteristics, for typical values.
T
ABLE
2. P
IN
C
HARACTERISTICS
Symbol
C
IN
R
PULLDOWN
R
PULLUP
Parameter
Input Capacitance
Input Pulldown Resistor
Input PullUP Resistor
Test Conditions
Minimum
Typical
4
51
51
Maximum
Units
pF
kΩ
kΩ
T
ABLE
3A. OE1 F
UNCTION
T
ABLE
Input
OE1
0
1
Outputs
Q0:Q4, nQ0:nQ4
Places outputs in Hi-Z state
Normal operation
T
ABLE
3B. OE2 F
UNCTION
T
ABLE
Input
OE2
0
1
Outputs
Q5:Q7, nQ5:nQ7
Places outputs in Hi-Z state
Normal operation
844008AYI-15
www.icst.com/products/hiperclocks.html
2
REV. B APRIL 28, 2006
PRELIMINARY
Integrated
Circuit
Systems, Inc.
ICS844008I-15
F
EMTO
C
LOCKS
™ C
RYSTAL
-
TO
-
LVDS F
REQUENCY
S
YNTHESIZER
4.6V
-0.5V to V
DD
+ 0.5V
10mA
15mA
-65°C to 150°C
NOTE: Stresses beyond those listed under Absolute
Maximum Ratings may cause permanent damage to the
device. These ratings are stress specifications only. Functional
operation of product at these conditions or any conditions be-
yond those listed in the
DC Characteristics
or
AC Character-
istics
is not implied. Exposure to absolute maximum rating
conditions for extended periods may affect product reliability.
A
BSOLUTE
M
AXIMUM
R
ATINGS
Supply Voltage, V
DD
Inputs, V
I
Outputs, I
O
Continuous Current
Surge Current
Storage Temperature, T
STG
Package Thermal Impedance,
θ
JA
47.9°C/W (0 lfpm)
T
ABLE
4A. P
OWER
S
UPPLY
DC C
HARACTERISTICS
,
V
DD
= 3.3V±5%, T
A
= -40°C
TO
85°C
Symbol
V
DD
V
DDA
I
DD
I
DDA
Parameter
Core Supply Voltage
Analog Supply Voltage
Power Supply Current
Analog Supply Current
Test Conditions
Minimum
3.135
3.135
Typical
3.3
3.3
122
11
Maximum
3.465
3.465
Units
V
V
mA
mA
T
ABLE
4B. LVCMOS / LVTTL DC C
HARACTERISTICS
,
V
DD
= 3.3V±5%, T
A
= -40°C
TO
85°C
Symbol
V
IH
V
IL
I
IH
I
IL
Parameter
Input High Voltage
Input Low Voltage
Input
High Current
Input
Low Current
MR, nPLL_SEL
OE1, OE2, F_SEL
MR, nPLL_SEL
OE1, OE2, F_SEL
Test Conditions
V
DD
= 3.3V
V
DD
= 3.3V
V
DD
= V
IN
= 3.465
V
DD
= V
IN
= 3.465
V
DD
= 3.465V, V
IN
= 0V
V
DD
= 3.465V, V
IN
= 0V
-5
-150
Minimum Typical
2
-0.3
Maximum
V
DD
+ 0.3
0.8
150
5
Units
V
V
µA
µA
µA
µA
T
ABLE
4C. LVDS DC C
HARACTERISTICS
,
V
DD
= 3.3V±5%, T
A
= -40°C
TO
85°C
Symbol
V
OD
Δ
V
OD
V
OS
Δ
V
OS
I
OZ
I
OFF
I
OSD
I
OS
Parameter
Differential Output Voltage
V
OD
Magnitude Change
Offset Voltage
V
OS
Magnitude Change
High Impedance Leakage Current
Power Off Leakage
Differential Output Shor t Circuit Current
Output Shor t Circuit Current
Test Conditions
Minimum
Typical
350
40
1.25
50
TBD
±1
-3.5
-3.5
Maximum
Units
mV
mV
V
mV
µA
µA
mA
mA
844008AYI-15
www.icst.com/products/hiperclocks.html
3
REV. B APRIL 28, 2006
PRELIMINARY
Integrated
Circuit
Systems, Inc.
ICS844008I-15
F
EMTO
C
LOCKS
™ C
RYSTAL
-
TO
-
LVDS F
REQUENCY
S
YNTHESIZER
Test Conditions
Minimum
22.4
Typical
25
Maximum
27.2
100
50
7
Units
MH z
ppm
Ω
pF
µW
T
ABLE
5. C
RYSTAL
C
HARACTERISTICS
Parameter
Mode of Oscillation
Frequency
Par ts per Million (ppm); NOTE 1
Equivalent Series Resistance (ESR)
Shunt Capacitance
Fundamental
Drive Level
100
NOTE: Characterized using an18pF parallel resonant crystal.
NOTE 1: When used with recommended 50ppm crystal and external trim caps adjusted for user PC board.
T
ABLE
6. AC C
HARACTERISTICS
,
V
DD
= 3.3V±5%, T
A
= -40°C
TO
85°C
Symbol
f
OUT
t
sk(o)
t
jit(cc)
t
jit(Ø)
t
R
/ t
F
Parameter
Output Frequency
Output Skew; NOTE 1, 2
Cycle-to-Cycle Jitter
RMS Phase Jitter (Random);
NOTE 3
Output Rise/Fall Time
125MHz, (1.875MHz - 20MHz)
100MHz, (1.875MHz - 20MHz)
20% to 80%
200
Test Conditions
FSEL = 0
FSEL = 1
Minimum
Typical
125
100
TBD
25
0.42
0.46
330
50
50
1
1
650
52
Maximum
Units
MHz
MHz
ps
ps
ps
ps
ps
%
odc
Output Duty Cycle
48
50
Minimum and Maximum values are design target specs.
NOTE 1: Defined as skew between outputs at the same supply voltages and with equal load conditions.
Measured at V
DD
/2.
NOTE 2: This parameter is defined in accordance with JEDEC Standard 65.
NOTE 3: Please refer to the Phase Noise Plot.
844008AYI-15
www.icst.com/products/hiperclocks.html
4
REV. B APRIL 28, 2006
PRELIMINARY
Integrated
Circuit
Systems, Inc.
ICS844008I-15
F
EMTO
C
LOCKS
™ C
RYSTAL
-
TO
-
LVDS F
REQUENCY
S
YNTHESIZER
AT
T
YPICAL
P
HASE
N
OISE
0
-10
-20
-30
-40
-50
-60
125MH
Z
A
T
3.3V
PCI Express Jitter Filter
125MHz
RMS Phase Jitter (Random)
1.875Mhz to 20MHz = 0.42ps (typical)
N
OISE
P
OWER
dBc
Hz
-70
-80
-90
-100
-110
Raw Phase Noise Data
-120
-130
-140
-150
-160
-170
-180
-190
1k
10k
➤
Phase Noise Result by adding
PCI Express Filter to raw data
100k
1M
10M
100M
O
FFSET
F
REQUENCY
(H
Z
)
844008AYI-15
www.icst.com/products/hiperclocks.html
5
➤
➤
REV. B APRIL 28, 2006
嵌入式系统
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