19-0297; Rev 1; 9/95
NUAL
KIT MA
ATION
HEET
EVALU
DATA S
LOWS
FOL
300Msps, 12-Bit DAC with
Complementary Voltage Outputs
____________________________Features
o
12-Bit Resolution
o
±1/2LSB Integral and Differential Nonlinearity
o
Capable of 300Msps Min Update Rate
o
Complementary 50Ω Outputs
o
Multiplying Reference Input
o
Low Glitch Energy (5.6pVs)
o
Single -5.2V Power Supply
o
On-Chip Data Registers
o
ECL-Compatible Inputs with Differential Clock
_______________General Description
The MAX555 is an advanced, monolithic, 12-bit digital-
to-analog converter (DAC) with complementary 50Ω
outputs. Fabricated using an oxide-isolated bipolar
process, the MAX555 is designed for signal-reconstruc-
tion applications at an output update rate of 300Msps.
It incorporates an analog multiplying function with
10MHz useable input bandwidth. The voltage-output
DAC uses precision laser trimming to achieve 12-bit
accuracy with ±1/2LSB integral and differential linearity
(±0.012% FS). Absolute gain error is a low 1% of full
scale. Full-scale transitions occur in less than 0.5ns.
Internal registers and a unique decoder reduce glitch-
ing and allow the MAX555 to achieve precise RF perfor-
mance with over 73dBc of spurious-free dynamic range
at 50Msps with f
OUT
= 3.1MHz, or 62dBc at 300Msps
with f
OUT
= 18.6MHz.
The MAX555 operates from a single -5.2V supply and
dissipates 980mW (nominal). It comes in a 68-pin ther-
mally enhanced PLCC package capable of accepting a
heatsink.
MAX555
______________Ordering Information
PART
MAX555CQK
TEMP. RANGE
0°C to +70°C
PIN-PACKAGE
68 Thermally
Enhanced PLCC
________________________Applications
Direct Digital Synthesis
Arbitrary Waveform Generation
HDTV/High-Resolution Graphics
Instrumentation
Communications Local Oscillators
Automated Tester Applications
Pin Configuration appears at end of data sheet.
___________________________________________________Simplified Block Diagram
CLK
CLK
800Ω
MAX555
LEVEL-SENSITIVE TRANSPARENT LATCH
800Ω
VREF
ROFFSET
VOUT
DECODED
BIT
LINES
50Ω
-20mA
LGND
AV
EE
50Ω
12-BIT
ECL
LINES
VOUT
BYPASS
________________________________________________________________
Maxim Integrated Products
1
Call toll free 1-800-998-8800 for literature.
300Msps, 12-Bit DAC with
Complementary Voltage Outputs
MAX555
ABSOLUTE MAXIMUM RATINGS
Analog Supply Voltage (AV
EE
) .................................-7V to +0.3V
Digital Supply Voltage (DV
EE
) ..................................-7V to +0.3V
Digital Input Voltage (D0–D11) ...................................-5.5V to 0V
Reference Input Voltage (V
IN
) .................................0V to +1.25V
Reference Input Current....................................0mA to +1.56mA
Output Compliance Voltage (V
OC
)......................-1.25V to +1.0V
Output Common-Mode Voltage (V
CM
) ................-0.25V to +1.0V
Note 1:
Typical thermal resistance, junction-to-case R
θJC
= 28°C/W.
Continuous Power Dissipation (T
A
= +70°C)
(without additional heatsink) ..............................................1.3W
Operating Temperature Range...............................0°C to +70°C
Junction Temperature Range (Note 1) .................0°C to +150°C
Storage Temperature Range .............................-65°C to +150°C
Lead Temperature (soldering, 10sec) .............................+300°C
See
Package Information.
Stresses beyond those listed under “Absolute Maximum Ratings” may cause permanent damage to the device. These are stress ratings only, and functional
operation of the device at these or any other conditions beyond those indicated in the operational sections of the specifications is not implied. Exposure to
absolute maximum rating conditions for extended periods may affect device reliability.
ELECTRICAL CHARACTERISTICS
(AV
EE
= DV
EE
= -5.2V, V
REF
= 1.000V, T
MIN
to T
MAX
= 0°C to +70°C, unless otherwise noted.) (Note 2.)
PARAMETER
DC ACCURACY
Differential Linearity Error
Integral Linearity Error
Absolute Gain Error
12-Bit Monotonicity
Output Offset Current
Output Leakage Current
I
OS
I
LEAK
D0–D11 = logic 1, V
REF
= 1.000V,
measured at VOUT
D0–D11 = logic 0, V
REF
= 0V,
measured at VOUT
90% to 10%, T
A
= +25°C
10% to 90%, T
A
= +25°C
Major carry, T
A
= +25°C
±0.1% FSR
±0.024% FSR, 1LSB change
f
OUT
= 5MHz, f
CLK
= 50MHz
f
OUT
= 10MHz, f
CLK
= 50MHz
f
OUT
= 20MHz, f
CLK
= 100MHz
f
OUT
= 30MHz, f
CLK
= 100MHz
f
OUT
= 30MHz, f
CLK
= 200MHz
f
OUT
= 40MHz, f
CLK
= 200MHz
f
OUT
= 40MHz, f
CLK
= 250MHz
f
OUT
= 50MHz, f
CLK
= 250MHz
f
OUT
= 40MHz, f
CLK
= 300MHz
f
OUT
= 50MHz, f
CLK
= 300MHz
Bits 0–11 high, T
A
= +25°C
DLE1
DLE2
ILE1
ILE2
EG
V
REF
= 1.000V, current out, into
virtual ground, end-point linearity
V
REF
= 1.000V, current out, into
virtual ground, end-point linearity
VOUT
VOUT
VOUT
VOUT
-0.012
-0.05
-0.012
-0.05
-1.0
±0.003
±0.01
±0.006
±0.01
±0.2
Guaranteed
40
3
100
50
µA
µA
0.012
0.05
0.012
0.05
1.0
% Full
Scale
% Full
Scale
% Full
Scale
SYMBOL
CONDITIONS
MIN
TYP
MAX
UNITS
V
REF
= 1.000V, voltage out, VOUT/VIN (Note 3)
TIME-DOMAIN PERFORMANCE (Note 4)
Fall Time
t
FALL
Rise Time
t
RISE
Glitch Energy
Settling Time
DYNAMIC PERFORMANCE (Notes 4, 5)
510
450
5.6
4
15
70
70
65
60
56
53
52
51
52
51
10.6
ps
ps
pVs
ns
Spurious-Free Dynamic Range
dBc
Output Noise
nV
√
Hz
2
_______________________________________________________________________________________
300Msps, 12-Bit DAC with
Complementary Voltage Outputs
ELECTRICAL CHARACTERISTICS (continued)
(AV
EE
= DV
EE
= -5.2V, V
REF
= 1.000V, T
MIN
to T
MAX
= 0°C to +70°C, unless otherwise noted.) (Note 2.)
PARAMETER
DIGITAL INPUTS
Input Current, Logic High
Input Current, Logic Low
Logic "1" Voltage
Logic "0" Voltage
DIGITAL TIMING
Data Update Rate
Data-to-Clock Setup Time
Data-to-Clock Hold Time
Clock-to-VOUT
Propagation Delay
LSBs Data-to-VOUT
Propagation Delay
MSBs Data-to-VOUT
Propagation Delay
MSBs Decode Delay
CONTROL AMPLIFIER
Amplifier Input Resistance
Multiplying Input Bandwidth
Open-Loop Gain
Input Offset Voltage
OUTPUT PERFORMANCE
Full-Scale Output Current
Output Resistance
Output Capacitance
POWER SUPPLIES
Analog Power-Supply Current
Digital Power-Supply Current
Power Dissipation
Package Thermal Resistance,
Junction to Ambient
f
D
t
SU
t
HOLD
t
PD3
t
PD2
t
PD1
t
DD
R
IN
BW
AV
OL
V
OS
I
OUT
R
OUT
C
OUT
AI
EE
DI
EE
PD
T
JA
Minimum data rate = DC (Note 6)
Bypass = 0, clocked mode (Notes 4, 7)
Bypass = 0, clocked mode (Notes 4, 7)
Bypass = 0, clocked mode (Notes 4, 7)
Bypass = 1, transparent mode (Notes 4, 7)
Bypass = 1, transparent mode (Notes 4, 7)
Bypass = 1, transparent mode (Notes 4, 7)
V
REF
= 1.000V
-3dB
T
A
= +25°C
T
A
= +25°C
V
REF
= 1.000V, R
L
= 0Ω
VOUT, VOUT
VOUT, VOUT
AV
EE
= DV
EE
= -5.2V
AV
EE
= DV
EE
= -5.2V
30
110
775
3
-250
19.0
49.5
300
1
1.8
2.0
1.5
2.1
600
800
10
20
0
20.0
50.0
15
46
150
0.98
28
60
190
1.3
825
MHz
ps
ns
ns
ns
ns
ps
Ω
MHz
kV/V
µV
mA
Ω
pF
mA
mA
W
°C/W
I
IH
I
IL
V
IH
V
IL
V
IH
= -0.75V
V
IL
= -1.95V
-1.1
-2.0
10
1
-0.75
-1.95
200
2
0
-1.48
µA
µA
V
V
SYMBOL
CONDITIONS
MIN
TYP
MAX
UNITS
MAX555
250
21.0
50.5
Note 2:
All devices are 100% production tested at +25°C and are guaranteed by design for T
A
= T
MIN
to T
MAX
as specified.
Note 3:
The gain-error method of calculation is shown below:
Definition:
[V
MEASURE(FS)
- V
IDEAL(FS)
] x 100
EG(%) = ––––––––––––––––––––––––––––––––––
V
IDEAL(FS)
where FS indicates full-scale measurements.
EG Method:
EG = [(4096 / 4095) V
MEASURE
- 16(V
REF
/ R
IN
) (R
OUT
)] x 100
–––––––––––––––––––––––––––––––––––––––––––––––––– %
16(V
REF
/ R
IN
) (R
OUT
)
= [(4096 / 4095) V
MEASURE
- 1] x 100
––––––––––––––––––––––––––––––––- %
1
where: V
REF
= 1.000V, R
IN
= 800Ω, R
OUT
= 50Ω, V
MEASURE
= VOUT (FS).
Note 4:
Dynamic and timing specifications are obtained from device characterization and simulation testing and are not production tested.
Note 5:
Spurious-free dynamic range is measured from the fundamental frequency to any harmonic or non-harmonic spurs within
the bandwidth f
CLK
/2, unless otherwise specified.
Note 6:
Guaranteed by design.
Note 7:
Timing definitions are detailed in Figure 2.
_______________________________________________________________________________________
3
300Msps, 12-Bit DAC with
Complementary Voltage Outputs
MAX555
__________________________________________Typical Operating Characteristics
(VREF = 0.75V, T
A
= +25°C, unless otherwise noted.)
SPURIOUS-FREE DYNAMIC RANGE
vs. f
OUT
(f
CLK
= 50MHz)
MAX555-01
SPURIOUS-FREE DYNAMIC RANGE
vs. f
OUT
(f
CLK
= 100MHz)
MAX555-02
SPURIOUS-FREE DYNAMIC RANGE
vs. f
OUT
(f
CLK
= 150MHz)
66
64
MAX555-03
72
70
68
66
64
62
60
0
2
4
6
8
72
70
68
66
64
62
60
68
SFDR (dBc)
SFDR (dBc)
SFDR (dBc)
62
60
58
56
54
52
10 12 14 16 18 20
0
5
10
15
20
25
0
5
10
15
20
25
30
35
40
f
OUT
(MHz)
f
OUT
(MHz)
f
OUT
(MHz)
SPURIOUS-FREE DYNAMIC RANGE
vs. f
OUT
(f
CLK
= 200MHz)
MAX555-04
SPURIOUS-FREE DYNAMIC RANGE
vs. f
OUT
(f
CLK
= 250MHz)
MAX555-05
SPURIOUS-FREE DYNAMIC RANGE
vs. f
OUT
(f
CLK
= 300MHz)
62
60
SFDR (dBc)
58
56
54
52
50
48
46
MAX555-06
68
66
64
SFDR (dBc)
68
66
64
62
SFDR (dBc)
60
58
56
54
52
64
62
60
58
56
54
52
0
5
10
15
20
25
30
35
40
f
OUT
(MHz)
50
48
0
5
10 15 20 25 30 35 40 45 50
f
OUT
(MHz)
0
10
20
30
f
OUT
(MHz)
40
50
60
SPURIOUS-FREE DYNAMIC RANGE
vs. f
CLK
(f
OUT
~ 1/16 f
CLK
)
MAX555-07
3RD HARMONIC DISTORTION vs.
V
REF
VOLTAGE (f
OUT
~ 1/5 f
CLK
)
MAX555-08
2ND HARMONIC DISTORTION vs.
V
REF
VOLTAGE (f
OUT
~ 1/5 f
CLK
)
f
CLK
= 300MHz
f
CLK
= 200MHz
MAX555-09
74
72
70
SFDR (dB)
68
66
64
62
60
58
50
100
150
200
250
300
-48
-50
-52
-54
-56
-58
-60
-62
-64
-66
-68
-70
-72
0.5
0.6
0.7
3RD HARMONIC (dBc)
f
CLK
= 300MHz
-48
-50
3RD HARMONIC (dBc)
-52
-54
-56
-58
-60
-62
-64
-66
-68
-70
-72
0.5
f
CLK
= 200MHz
f
CLK
= 100MHz
f
CLK
= 100MHz
0.8
0.9
1.0
350
0.6
0.7
0.8
0.9
1.0
CLOCK FREQUENCY (MHz)
V
REF
VOLTAGE (V)
V
REF
VOLTAGE (V)
4
_______________________________________________________________________________________
300Msps, 12-Bit DAC with
Complementary Voltage Outputs
_____________________Pin Description
PIN
NAME
BYPASS
CLK
CLK
DGND
DV
EE
FUNCTION
Disables latching of data
when high (ECL input)
Data Clock (ECL input)
Data Clock Not (ECL input)
Digital Signal Grounds
-5.2V Digital Power Supplies
_______________Detailed Description
Figure 1’s functional diagram shows the MAX555’s three
major divisions: a digital section, a control-amplifier sec-
tion, and a resistor-divider network. The digital section
consists of a master/slave register, decoding logic, and
current switches. The control-amplifier section includes a
control amplifier and an array of 23 current sources divid-
ed into three groups. The resistor divider scales the cur-
rents from these groups to achieve the correct binary
weighting at the output. The output of the resistor-divider
network is laser trimmed to 50Ω, a key feature for driving
into controlled impedance transmission lines.
The first group of current sources comprises the six
MSBs, D11–D6 (resulting in 15 identical, plus two binary
weighted currents), which are applied directly to the out-
put of the resistor-divider network. The second group,
bits D5–D3 (three binary weighted currents), is applied
to the middle of the divider network. The middle of the
network divides the current seen at the output by 8. The
third group, bits D2–D0 (three additional binary weighted
current sources), is applied to the input of the resistive
network, dividing the current seen at the output by 64.
Glitching is reduced by decoding the four MSBs into 15
identical current sources and synchronizing data with a
master/slave register at every current switch. Data bits
are transferred to the output on the positive-going edge
of the clock, with the BYPASS input asserted low. In
the asynchronous mode with the BYPASS input assert-
ed high, the latches are transparent and data is trans-
ferred to the output regardless of the clock state. All
digital inputs are ECL compatible. The clock input is
differential.
The control amplifier forces a reference current, which is
replicated in the current sources. This reference current
is nominally 1.25mA. It can be supplied by an external
current source, or by an external voltage source of
1.000V applied to the VREF input.
A reference input of V
REF
= 1.000V will produce a full-
scale output voltage of V
FS
= -1.000V, where:
V
FS
= 4096 / 4095 x VOUT (code 0)
for the VOUT output. The output coding is summarized
in Table 1.
The DAC’s control amplifier has a typical open-loop volt-
age gain of 85dB, and its gain-magnitude bandwidth is
flat up to 10MHz. When the control amplifier is not being
used for high-speed multiplying applications, it is recom-
mended that a 0.4µF capacitor be connected from LBIAS
to AV
EE
to increase control-amplifier stability and reduce
current-source noise.
MAX555
1
2
3
4, 56, 57,
63, 66
5, 55
10, 11, 12,
21–25, 27,
31, 36, 37,
40, 41, 43,
45, 46, 61
13, 14
15, 16
17, 18
19, 49, 51,
52, 53, 68
20, 29, 30,
48
26, 44
N.C.
No Connection
VOUT
LGND
VOUT
TN
AGND
HS
DAC Outputs
Ladder Grounds
DAC Output Complements
Test Node—internal test point,
do not connect
Analog Signal Grounds
Heatspreader Connections—
bypass with 0.1µF to AV
EE
PTAT-IB Reference
Compensation Output (con-
nect bypass capacitor to
AV
EE
)
Test node—must connect to
AGND
-5.2V Analog Power Supplies
Analog Reference Voltage
Center-Tap Input
Analog Reference Voltage
Inputs (Kelvin connection)
Offset Compensation Input
Control-Amplifier PTAT
Reference Compensation
Input (connect bypass capaci-
tor to AV
EE
)
Ladder-Bias Alternate
Compensation Output (con-
nect bypass capacitor to AV
EE
)
Data Words (ECL inputs)
28
ALTCOMPIB
32
33, 34
35
38, 39
42
47
LOOPCRNT
AV
EE
VREF/2
VREF
ROFFSET
ALTCOMPC
50
54, 58, 59,
60, 62, 64,
65, 67, 6,
7, 8, 9
LBIAS
D11(MSB)–
D0(LSB)
_______________________________________________________________________________________
5
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