19-2999; Rev 0; 10/03
KIT
ATION
EVALU
E
BL
AVAILA
Dual, 10-Bit, 300Msps, DAC with 4x/2x/1x
Interpolation Filters and PLL
General Description
The MAX5858A dual, 10-bit, 300Msps digital-to-analog
converter (DAC) provides superior dynamic performance
in wideband communication systems. The MAX5858A
integrates two 10-bit DAC cores, 4x/2x/1x programmable
digital interpolation filters, phase-lock loop (PLL) clock
multiplier, and a 1.24V reference. The MAX5858A sup-
ports single-ended and differential modes of operation.
The MAX5858A dynamic performance is maintained over
the entire power-supply operating range of 2.7V to 3.3V.
The analog outputs support a compliance voltage of
-1.0V to +1.25V.
The 4x/2x/1x programmable interpolation filters feature
excellent passband distortion and noise performance.
Interpolating filters minimize the design complexity of
analog reconstruction filters while lowering the data bus
and the clock speeds of the digital interface. The PLL
multiplier generates all internal, synchronized high-
speed clock signals for interpolating filter operation and
DAC core conversion. The internal PLL helps minimize
system complexity and lower cost. To reduce the I/O pin
count, the DAC can also operate in interleave data
mode. This allows the MAX5858A to be updated on a
single 10-bit bus.
The MAX5858A features digital control of channel gain
matching to within ±0.4dB in sixteen 0.05dB steps.
Channel matching improves sideband suppression in
analog quadrature modulation applications. The on-
chip 1.24V bandgap reference includes a control
amplifier that allows external full-scale adjustments of
both channels through a single resistor. The internal ref-
erence can be disabled and an external reference can
be applied for high-accuracy applications.
The MAX5858A features full-scale current outputs of
2mA to 20mA and operates from a 2.7V to 3.3V single
supply. The DAC supports three modes of power-con-
trol operation: normal, low-power standby, and com-
plete power-down. In power-down mode, the operating
current is reduced to 1µA.
The MAX5858A is packaged in a 48-pin TQFP with
exposed paddle (EP) for enhanced thermal dissipation
and is specified for the extended (-40°C to +85°C) opera-
ting temperature range.
Features
o
10-Bit Resolution, Dual DAC
o
300Msps Update Rate
o
Integrated 4x/2x/1x Interpolating Filters
o
Internal PLL Multiplier
o
2.7V to 3.3V Single Supply
o
Full Output Swing and Dynamic Performance at
2.7V Supply
o
Superior Dynamic Performance
73dBc SFDR at f
OUT
= 20MHz
UMTS ACLR = 63dB at f
OUT
= 30.7MHz
o
Programmable Channel Gain Matching
o
o
o
o
o
Integrated 1.24V Low-Noise Bandgap Reference
Single-Resistor Gain Control
Interleave Data Mode
Differential Clock Input Modes
EV Kit Available—MAX5858AEVKit
MAX5858A
Ordering Information
PART
MAX5858AECM
TEMP RANGE
-40°C to +85°C
PIN-PACKAGE
48 TQFP-EP*
*EP
= Exposed paddle.
Pin Configuration
OUTPA
OUTNA
AGND
OUTPB
OUTNB
DVDD
DGND
AVDD
AVDD
REFR
N.C.
N.C.
48 47 46 45 44 43 42 41 40 39 38 37
DA9/PD
DA8/DACEN
DA7/F2EN
DA6/F1EN
DA5/G3
DGND
DVDD
DA4/G2
DA3/G1
DA2/G0
DA1
DA0
Applications
Communications
SatCom, LMDS, MMDS, HFC, DSL, WLAN,
Point-to-Point Microwave Links
Wireless Base Stations
Direct Digital Synthesis
Instrumentation/ATE
1
2
3
4
5
6
7
8
9
10
11
12
EP
MAX5858A
36
35
34
33
32
31
30
29
28
27
26
25
REFO
REN
PLLF
PGND
PVDD
CLKXN
CLKXP
PLLEN
LOCK
CW
DB0
DB1
13 14 15 16 17 18 19 20 21 22 23 24
DB5
DVDD
DGND
DB7
DB6
DB9
TQFP-EP
NOTE:
EXPOSED PADDLE CONNECTED TO GND.
________________________________________________________________
Maxim Integrated Products
IDE
DB4
DB3
DB2
DB8
CLK
1
For pricing, delivery, and ordering information, please contact Maxim/Dallas Direct! at
1-888-629-4642, or visit Maxim’s website at www.maxim-ic.com.
Dual, 10-Bit, 300Msps, DAC with 4x/2x/1x
Interpolation Filters and PLL
MAX5858A
ABSOLUTE MAXIMUM RATINGS
AV
DD
, DV
DD
, PV
DD
to AGND, DGND, PGND ..........-0.3V to +4V
DA9–DA0, DB9–DB0,
CW, REN,
PLLF, PLLEN to AGND,
DGND, PGND........................................................-0.3V to +4V
IDE to AGND, DGND, PGND ...................-0.3V to (DV
DD
+ 0.3V)
CLKXN, CLKXP to PGND .........................................-0.3V to +4V
OUTP_, OUTN_ to AGND.......................-1.25V to (AV
DD
+ 0.3V)
CLK, LOCK to DGND...............................-0.3V to (DV
DD
+ 0.3V)
REFR, REFO to AGND .............................-0.3V to (AV
DD
+ 0.3V)
AGND to DGND, DGND to PGND,
AGND to PGND ..................................................-0.3V to +0.3V
Maximum Current into Any Pin
(excluding power supplies) ............................................±50mA
Continuous Power Dissipation (T
A
= +70°C)
48-Pin TQFP-EP (derate 36.2mW/°C above +70°C) ....2.899W
Operating Temperature Range ...........................-40°C to +85°C
Storage Temperature Range .............................-65°C to +150°C
Junction Temperature ......................................................+150°C
Lead Temperature (soldering, 10s) .................................+300°C
Stresses beyond those listed under “Absolute Maximum Ratings” may cause permanent damage to the device. These are stress ratings only, and functional
operation of the device at these or any other conditions beyond those indicated in the operational sections of the specifications is not implied. Exposure to
absolute maximum rating conditions for extended periods may affect device reliability.
ELECTRICAL CHARACTERISTICS
(AV
DD
= DV
DD
= PV
DD
= 3V, AGND = DGND = PGND = 0, f
DAC
= 165Msps, no interpolation, PLL disabled, external reference,
V
REFO
= 1.2V, I
FS
= 20mA, output amplitude = 0dB FS, differential output, T
A
= T
MIN
to T
MAX
, unless otherwise noted. T
A
> +25°C
guaranteed by production test. T
A
< +25°C guaranteed by design and characterization. Typical values are at T
A
= +25°C.)
PARAMETER
STATIC PERFORMANCE
Resolution
Integral Nonlinearity
Differential Nonlinearity
Offset Error
Gain Error (See
Gain Error
Parameter Definitions
Section)
DYNAMIC PERFORMANCE
Maximum DAC Update Rate
Glitch Impulse
f
OUT
= 5MHz,
T
A
≥
+25°C
f
DAC
= 165Msps
Spurious-Free Dynamic Range to
Input Update Rate Nyquist
SFDR
f
DAC
= 300Msps,
2x interpolation
f
OUT
= 20MHz
f
OUT
= 50MHz
f
OUT
= 70MHz
f
OUT
= 5MHz
f
OUT
= 40MHz
f
OUT
= 60MHz
Spurious-Free Dynamic Range
Within a Window
f
DAC
= 200Msps, 2x interpolation,
f
OUT
= 40MHz, span = 20MHz
f
DAC
= 165Msps, f
OUT
= 5MHz,
span = 4MHz
MTPR
ACLR
f
DAC
= 165Msps, f
OUT
= 20MHz
f
DAC
=122.88Msps, f
OUT
= 30.72MHz
76.5
68
f
DAC
4x/2x interpolation modes
300
5
76
73
66
65
76
73
72
85
dBc
85
76
63
dBc
dB
dBc
Msps
pV-s
INL
DNL
V
OS
GE
Internal reference (Note 1)
External reference
R
L
= 0
Guaranteed monotonic, R
L
= 0
10
-1.25
-0.75
-0.5
-10
-8
±0.5
±0.25
±0.1
±1.6
±1.2
+1.25
+0.75
+0.5
+11
+8
Bits
LSB
LSB
LSB
%
SYMBOL
CONDITIONS
MIN
TYP
MAX
UNITS
SFDR
Multitone Power Ratio, 8 Tones,
~300kHz Spacing
Adjacent Channel Leakage Ratio
with UMTS
2
_______________________________________________________________________________________
Dual, 10-Bit, 300Msps, DAC with 4x/2x/1x
Interpolation Filters and PLL
ELECTRICAL CHARACTERISTICS (continued)
(AV
DD
= DV
DD
= PV
DD
= 3V, AGND = DGND = PGND = 0, f
DAC
= 165Msps, no interpolation, PLL disabled, external reference,
V
REFO
= 1.2V, I
FS
= 20mA, output amplitude = 0dB FS, differential output, T
A
= T
MIN
to T
MAX
, unless otherwise noted. T
A
> +25°C
guaranteed by production test. T
A
< +25°C guaranteed by design and characterization. Typical values are at T
A
= +25°C.)
PARAMETER
Total Harmonic Distortion to
Nyquist
Noise Spectral Density
Output Channel-to-Channel
Isolation
Gain Mismatch Between
Channels
Phase Mismatch Between
Channels
Wideband Output Noise
ANALOG OUTPUT
Full-Scale Output Current Range
Output Voltage Compliance
Range
Output Leakage Current
REFERENCE
Reference Output Voltage
Output-Voltage Temperature Drift
Reference Output Drive
Capability
Reference Input Voltage Range
Reference Supply Rejection
Current Gain
I
FS
/I
REF
-0.005dB
Passband Width
f
OUT
/
0.5f
DAC
-0.01dB
-0.1dB
-3dB
0.604f
DAC
/ 2 to 1.396f
DAC
/ 2
Stopband Rejection
0.600f
DAC
/ 2 to 1.400f
DAC
/ 2
0.594f
DAC
/ 2 to 1.406f
DAC
/ 2
0.532f
DAC
/ 2 to 1.468f
DAC
/ 2
Group Delay
INTERPOLATION FILTER (2x interpolation)
0.398
0.402
0.419
0.478
74
62
53
14
18
Data
clock
cycles
Data
clock
cycles
dB
MHz/
MHz
REN
= AV
DD
0.10
0.2
32
V
REF0
TCV
REF
REN
= AGND
1.14
1.24
±50
50
1.32
1.34
V
ppm/°C
µA
V
mV/V
mA/mA
Power-down or standby mode
I
FS
2
-1.0
-5
20
+1.25
+5
mA
V
µA
SYMBOL
THD
n
D
CONDITIONS
f
DAC
= 165Msps, f
OUT
= 5MHz
f
DAC
= 165Msps, f
OUT
= 5MHz
f
OUT
= 5MHz
f
OUT
= 5MHz
f
OUT
= 5MHz
MIN
TYP
-72
-143
80
±0.05
±0.15
50
MAX
UNITS
dBc
dBm/Hz
dB
dB
Degrees
pA/√Hz
MAX5858A
Impulse Response Duration
22
_______________________________________________________________________________________
3
Dual, 10-Bit, 300Msps, DAC with 4x/2x/1x
Interpolation Filters and PLL
MAX5858A
ELECTRICAL CHARACTERISTICS (continued)
(AV
DD
= DV
DD
= PV
DD
= 3V, AGND = DGND = PGND = 0, f
DAC
= 165Msps, no interpolation, PLL disabled, external reference,
V
REFO
= 1.2V, I
FS
= 20mA, output amplitude = 0dB FS, differential output, T
A
= T
MIN
to T
MAX
, unless otherwise noted. T
A
> +25°C
guaranteed by production test. T
A
< +25°C guaranteed by design and characterization. Typical values are at T
A
= +25°C.)
PARAMETER
SYMBOL
-0.005dB
Passband Width
f
OUT
/
0.5f
DAC
-0.01dB
-0.1dB
-3dB
0.302f
DAC
/ 2 to 1.698f
DAC
/ 2
Stopband Rejection
0.300f
DAC
/ 2 to 1.700f
DAC
/ 2
0.297f
DAC
/ 2 to 1.703 f
DAC
/ 2
0.266f
DAC
/ 2 to 1.734f
DAC
/ 2
Group Delay
CONDITIONS
MIN
TYP
0.200
0.201
0.210
0.239
74
63
53
14
22
Data
clock
cycles
Data
clock
cycles
V
0.8
V
IH
= 2V
V
IL
= 0.8V
-1
-1
3
0.9
×
DV
DD
0.1
×
DV
DD
PV
DD
/ 2
0.5
Single-ended clock drive
No interpolation
Input Data Rate
f
DATA
2x interpolation
4x interpolation
PLL disabled
PLL enabled
PLL disabled
PLL enabled
37.5
75
37.5
75
5
165
150
150
75
75
165
150
75
MHz
Msps
+1
+1
V
µA
µA
pF
dB
MHz/
MHz
MAX
UNITS
INTERPOLATION FILTER (4x interpolation)
Impulse Response Duration
LOGIC INPUTS (IDE,
CW, REN,
DA9–DA0, DB9–DB0, PLLEN)
Digital Input-Voltage High
Digital Input-Voltage Low
Digital Input-Current High
Digital Input-Current Low
Digital Input Capacitance
DIGITAL OUTPUTS (CLK, LOCK)
Digital Output-Voltage High
Digital Output-Voltage Low
V
OH
V
OL
I
SOURCE
= 0.5mA, Figure 1
I
SINK
= 0.5mA, Figure 1
V
IH
V
IL
I
H
I
IL
C
IN
2
27
V
V
DIFFERENTIAL CLOCK INPUT (CLKXP, CLKXN)
Clock Input Internal Bias
Differential Clock Input Swing
Clock Input Impedance
TIMING CHARACTERISTICS
V
V
P-P
kΩ
No interpolation, PLL enabled
Clock Frequency at CLK Input
f
CLK
2x interpolation, PLL enabled
4x interpolation, PLL enabled
4
_______________________________________________________________________________________
Dual, 10-Bit, 300Msps, DAC with 4x/2x/1x
Interpolation Filters and PLL
ELECTRICAL CHARACTERISTICS (continued)
(AV
DD
= DV
DD
= PV
DD
= 3V, AGND = DGND = PGND = 0, f
DAC
= 165Msps, no interpolation, PLL disabled, external reference,
V
REFO
= 1.2V, I
FS
= 20mA, output amplitude = 0dB FS, differential output, T
A
= T
MIN
to T
MAX
, unless otherwise noted. T
A
> +25°C
guaranteed by production test. T
A
< +25°C guaranteed by design and characterization. Typical values are at T
A
= +25°C.)
PARAMETER
Output Settling Time
Output Rise Time
Output Fall Time
Data-to-CLK Rise Setup Time
(Note 3)
Data-to-CLK Rise Hold Time
(Note 3)
Data-to-CLK Fall Setup Time
(Note 3)
Data-to-CLK Fall Hold Time
(Note 3)
Control Word to
CW
Fall Setup
Time
Control Word to
CW
Fall Hold
Time
CW
High Time
CW
Low Time
DACEN Rise-to-V
OUT
Stable
PD Fall-to-V
OUT
Stable
Clock Frequency at
CLKXP/CLKXN Input
CLKXP/CLKXN Differential Clock
Input to CLK Output Delay
Minimum CLKXP/CLKXN Clock
High Time
Minimum CLKXP/CLKXN Clock
Low Time
POWER REQUIREMENTS
Analog Power-Supply Voltage
Analog Supply Current
Digital Power-Supply Voltage
AV
DD
I
AVDD
DV
DD
(Note 4)
2.7
2.7
45
3.3
49
3.3
V
mA
V
t
STB
t
PDSTB
f
CLKDIFF
t
CXD
t
CXH
t
CXL
External reference
Differential clock, PLL disabled
PLL disabled
4.6
1.5
1.5
t
DCSR
t
DCHR
t
DCSF
t
DCHF
t
CWS
t
CWH
SYMBOL
t
s
CONDITIONS
To ±0.1% error band (Note 2)
10% to 90% (Note 2)
90% to 10% (Note 2)
PLL disabled
PLL enabled
PLL disabled
PLL enabled
PLL disabled
PLL enabled
PLL disabled
PLL enabled
1.5
2.2
0.4
1.4
1.8
2.4
1.2
1.3
2.5
2.5
5
5
0.7
0.5
300
MIN
TYP
11
2.5
2.5
MAX
UNITS
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
µs
ms
MHz
ns
ns
ns
MAX5858A
_______________________________________________________________________________________
5
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