MAX6023EBTxx
Rev. A
RELIABILITY REPORT
FOR
MAX6023EBTxx
CHIP SCALE DEVICES
July 17, 2003
MAXIM INTEGRATED PRODUCTS
120 SAN GABRIEL DR.
SUNNYVALE, CA 94086
Written by
Reviewed by
Jim Pedicord
Quality Assurance
Reliability Lab Manager
Bryan J. Preeshl
Quality Assurance
Executive Director
Conclusion
The MAX6023 successfully meets the quality and reliability standards required of all Maxim products. In addition,
Maxim’s continuous reliability monitoring program ensures that all outgoing product will continue to meet Maxim’s quality
and reliability standards.
Table of Contents
I. ........Device Description
II. ........Manufacturing Information
III. .......Packaging Information
IV. .......Die Information
V. ........Quality Assurance Information
VI. .......Reliability Evaluation
......Attachments
I. Device Description
A. General
The MAX6023 is a family of low-dropout, micropower voltage references in a 5-bump, chip-scale package (UCSP™).
The MAX6023 series-mode (three-terminal) references, which operate with input voltages from 2.5V to 12.6V (1.25V
and 2.048V options) or (V
OUT
+ 0.2V) to 12.6V (all other voltage options), are available with output voltage options of
1.25V, 2.048V, 2.5V, 3.0V, 4.096V, 4.5V, and 5.0V. These devices are guaranteed an initial accuracy of ±0.2% and
30ppm/°C temperature drift over the -40°C to +85°C extended temperature range.
UCSPs offer the benefit of moving to smaller footprint and lower profile devices, significantly smaller than even SC70
or SOT23 plastic surface-mount packages. The significantly lower profile (compared to plastic SMD packages) of the
UCSP makes the device ideal for height-critical applications. Miniature UCSP packages also enable device
placement close to sources and allow more flexibility in a complex or large design layout.
The MAX6023 voltage references use only 27µA of supply current. And unlike shunt-mode (two-terminal) references,
the supply current of the MAX6023 family varies only 0.8µA/V with supply-voltage changes, translating to longer
battery life. Additionally, these internally compensated devices do not require an external compensation capacitor
and are stable up to 2.2nF of load capacitance. The low-dropout voltage and the low supply current make these
devices ideal for battery-operated systems.
B. Absolute Maximum Ratings
Item
(Voltages Referenced to GND)
IN
OUT
Output Short Circuit to GND or IN (VIN < 6V)
Output Short Circuit to GND or IN (VIN = 6V)
Operating Temperature Range
Storage Temperature Range
Bump Temperature (soldering, 10s)
Continuous Power Dissipation
5-Bump UCSP
Derates above +70°C
5-Bump UCSP
Rating
-0.3V to +13.5V
-0.3V to (VIN + 0.3V)
Continuous
60s
-40°C to +85°C
-65°C to +150°C
+300°C
273mW
2.4mW/°C
Note 1:
This device is constructed using a unique set of packaging techniques that impose a limit on the thermal
profile the device can be exposed to during board-level solder attach and rework. This limit permits only the use of
solder profiles recommended in the industry-standard specification, JEDEC 020A, paragraph 7.6, Table 3 for IR/VPR
and convection reflow. Preheating is required. Hand or wave soldering is not allowed.
II. Manufacturing Information
A. Description/Function:
B. Process:
C. Number of Device Transistors:
D. Fabrication Location:
E. Assembly Location:
F. Date of Initial Production:
Precision, Low-Power, Low-Dropout, UCSP Voltage Reference
S12 (Standard 1.2 micron silicon gate CMOS)
70
Oregon, USA
Philippines or USA
January, 2001
III. Packaging Information
A. Package Type:
B. Lead Frame:
C. Lead Finish:
D. Die Attach:
E. Bondwire:
F. Mold Material:
G. Assembly Diagram:
H. Flammability Rating:
I. Classification of Moisture Sensitivity
per JEDEC standard JESD22-112:
5-Bump UCSP
N/A
N/A
N/A
N/A
N/A
# 05-0901-0164
Class UL94-V0
Level 1
IV. Die Information
A. Dimensions:
B. Passivation:
C. Interconnect:
D. Backside Metallization:
E. Minimum Metal Width:
F. Minimum Metal Spacing:
G. Bondpad Dimensions:
H. Isolation Dielectric:
I. Die Separation Method:
63 x 43 mils
SiN/SiO (nitride/oxide)
Aluminum/Si (Si = 1%)
None
1.2 microns (as drawn)
1.2 microns (as drawn)
5 mil. Sq.
SiO
2
Wafer Saw
V. Quality Assurance Information
A. Quality Assurance Contacts:
Jim Pedicord (Manager, Reliability Operations)
Bryan Preeshl (Executive Director)
Kenneth Huening (Vice President)
0.1% for all electrical parameters guaranteed by the Datasheet.
0.1% For all Visual Defects.
B. Outgoing Inspection Level:
C. Observed Outgoing Defect Rate: < 50 ppm
D. Sampling Plan: Mil-Std-105D
VI. Reliability Evaluation
A. Accelerated Life Test
The results of the 135°C biased (static) life test are shown in
Table 1.
Using these results, the Failure
Rate (λ) is calculated as follows:
λ
=
1
=
MTTF
1.83
192 x 4389 x 57 x 2
(Chi square value for MTTF upper limit)
Temperature Acceleration factor assuming an activation energy of 0.8eV
λ
= 19.05 x 10
-9
λ
= 19.05 F.I.T. (60% confidence level @ 25°C)
This low failure rate represents data collected from Maxim’s reliability monitor program. In addition to
routine production Burn-In, Maxim pulls a sample from every fabrication process three times per week and subjects
it to an extended Burn-In prior to shipment to ensure its reliability. The reliability control level for each lot to be
shipped as standard product is 59 F.I.T. at a 60% confidence level, which equates to 3 failures in an 80 piece
sample. Maxim performs failure analysis on any lot that exceeds this reliability control level. Attached Burn-In
Schematic (Spec. # 06-5114) shows the static Burn-In circuit. Maxim also performs quarterly 1000 hour life test
monitors. This data is published in the Product Reliability Report (RR-1M).
B. Moisture Resistance Tests
Maxim pulls pressure pot samples from every assembly process three times per week. Each lot sample
must meet an LTPD = 20 or less before shipment as standard product. Additionally, the industry standard
85°C/85%RH testing is done per generic device/package family once a quarter.
C. E.S.D. and Latch-Up Testing
The RF39 die type has been found to have all pins able to withstand a transient pulse of
±1500V,
per Mil-
Std-883 Method 3015 (reference attached ESD Test Circuit). Latch-Up testing has shown that this device
withstands a current of
±250mA.
Table 1
Reliability Evaluation Test Results
MAX6034EBTxx
TEST ITEM
TEST CONDITION
FAILURE
IDENTIFICATION
SAMPLE
SIZE
NUMBER OF
FAILURES
PACKAGE
Static Life Test
(Note 1)
Ta = 135°C
Biased
Time = 192 hrs.
Moisture Testing
(Note 2)
Pressure Pot
Ta = 121°C
P = 15 psi.
RH= 100%
Time = 168hrs.
Ta = 85°C
RH = 85%
Biased
Time = 1000hrs.
DC Parameters
& functionality
77
0
DC Parameters
& functionality
UCSP
77
0
85/85
DC Parameters
& functionality
N/A
N/A
Mechanical Stress
(Note 2)
Temperature
Cycle
-40°C/125°C
1000 Cycles
Slow Ramp (Note 3)
DC Parameters
QFN
UCSP
77
77
0
0
Note 1: Life Test Data may represent plastic DIP qualification lots.
Note 2: Generic Package/Process data
Note 3: UCSP Temperature Cycle performed at with a ramp rate of 11°C/minute, dwell=15 minutes, one cycle/hour
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