VCXO Jitter Attenuator & FemtoClock Multiplier
®
ICS813252DI-02
DATA SHEET
General Description
The ICS813252DI-02 is a PLL based synchronous multiplier that is
optimized for PDH or SONET to Ethernet clock jitter attenuation and
frequency translation. The device contains two internal frequency
multiplication stages that are cascaded in series. The first stage is a
VCXO PLL that is optimized to provide reference clock jitter
attenuation. The second stage is a FemtoClock
®
frequency multiplier
that provides the low jitter, high frequency Ethernet output clock that
easily meets Gigabit and 10 Gigabit Ethernet jitter requirements.
Pre-divider and output divider multiplication ratios are selected using
device selection control pins. The multiplication ratios are optimized
to support most common clock rates used in PDH, SONET and
Ethernet applications. The VCXO requires the use of an external,
inexpensive pullable crystal. The VCXO uses external passive loop
filter components which allows configuration of the PLL loop
bandwidth and damping characteristics. The device is packaged in a
space-saving 32-VFQFN package and supports industrial
temperature range.
Features
•
•
•
•
•
•
•
•
•
•
•
•
Two LVPECL outputs
Each output supports independent frequency selection at 25MHz,
125MHz, 156.25MHz and 312.5MHz
Two differential inputs support the following input types: LVPECL,
LVDS, LVHSTL, SSTL, HCSL
Accepts input frequencies from 8kHz to 155.52MHz including
8kHz, 1.544MHz, 2.048MHz, 19.44MHz, 25MHz, 77.76MHz,
125MHz and 155.52MHz
Attenuates the phase jitter of the input clock by using a low-cost
pullable fundamental mode VCXO crystal
VCXO PLL bandwidth can be optimized for jitter attenuation and
reference tracking
using external loop filter connection
FemtoClock frequency multiplier provides low jitter, high
frequency output
Absolute pull range: 50ppm
FemtoClock VCO frequency: 625MHz
RMS phase jitter @125MHz, using a 25MHz crystal
(10kHz - 20MHz): 1.04ps (typical)
3.3V supply voltage
-40°C to 85°C ambient operating temperature
Available in lead-free (RoHS 6) package
Pin Assignment
XTAL_OUT
XTAL_IN
nCLK0
CLK0
nCLK1
CLK1
V
CCX
32 31 30 29 28 27 26 25
LF1
LF0
ISET
V
EE
CLK_SEL
V
CC
RESERVED
V
EE
1
2
3
4
5
6
7
8
9 10 11 12 13 14 15 16
ODBSEL_1
ODBSEL_0
ODASEL_1
PDSEL_1
PDSEL_2
PDSEL_0
V
CC
V
CCA
V
CC
24
23
22
21
20
19
18
17
V
EE
nQB
QB
V
CCO
nQA
QA
V
EE
ODASEL_0
ICS813252DI-02
32 Lead VFQFN
5mm x 5mm x 0.925mm package body
K Package
Top View
ICS813252DKI-02 REVISION A JANUARY 25, 2011
1
©2011 Integrated Device Technology, Inc.
ICS813252DI-02 Data Sheet
VCXO JITTER ATTENUATOR & FEMTOCLOCK
®
MULTIPLIER
Block Diagram
XTAL_OUT
25MHz
ISET
LF0
LF1
XTAL_IN
Loop
Filter
Output Divider
PDSEL_[2:0]
Pullup
QA
nQA
CLK0
nCLK0
0
VCXO Input
Pre-Divider
000 = 1
001 = 193
010 = 256
011 = 2430
100 = 3125
101 = 9720
110 = 15625
111 = 19440
(default)
Phase
Detector
00 = 25
(default)
01 = 5
10 = 4
11 = 2
2
VCXO
Charge
Pump
CLK1
nCLK1
CLK_SEL
Pulldown
FemtoClock PLL
625MHz
Output Divider
00 = 25
(default)
01 = 5
10 = 4
11 = 2
2
ODASEL_[1:0]
1
VCXO Feedback Divider
÷3125
QB
nQB
VCXO Jitter Attenuation PLL
ODBSEL_[1:0]
ICS813252DKI-02 REVISION A JANUARY 25, 2011
2
©2011 Integrated Device Technology, Inc.
ICS813252DI-02 Data Sheet
VCXO JITTER ATTENUATOR & FEMTOCLOCK
®
MULTIPLIER
Table 1. Pin Descriptions
Number
1, 2
3
4, 8, 18, 24
5
6, 12, 27
7
9,
10,
11
13
14,
15
16,
17
19, 20
21
22, 23
25
26
28
29
30,
31
32
Name
LF1, LF0
ISET
V
EE
CLK_SEL
V
CC
RESERVED
PDSEL_2,
PDSEL_1,
PDSEL_0
V
CCA
ODBSEL_1,
ODBSEL_0
ODASEL_1,
ODASEL_0
QA, nQA
V
CCO
QB, nQB
nCLK1
CLK1
nCLK0
CLK0
XTAL_OUT,
XTAL_IN
V
CCX
Type
Analog
Input/Output
Analog
Input/Output
Power
Input
Power
Reserve
Input
Power
Input
Input
Output
Power
Output
Input
Input
Input
Input
Input
Power
Pullup/
Pulldown
Pulldown
Pullup/
Pulldown
Pulldown
Pulldown
Pulldown
Pullup
Pulldown
Description
Loop filter connection node pins. LF0 is the output. LF1 is the input.
Charge pump current setting pin.
Negative supply pins.
Input clock select. When HIGH selects CLK1, nCLK1. When LOW, selects
CLK0, nCLK0. LVCMOS / LVTTL interface levels.
Core supply pins.
Reserved pin. Do not connect.
Pre-divider select pins. LVCMOS/LVTTL interface levels.
See Table 3A.
Analog supply pin.
Frequency select pins for Bank B output. See Table 3B. LVCMOS/LVTTL
interface levels.
Frequency select pins for Bank A output. See Table 3B. LVCMOS/LVTTL
interface levels.
Differential Bank A clock outputs. LVPECL interface levels.
Output supply pin.
Differential Bank B clock outputs. LVPECL interface levels.
Inverting differential clock input. V
CC
/2 bias voltage when left floating.
Non-inverting differential clock input.
Inverting differential clock input. V
CC
/2 bias voltage when left floating.
Non-inverting differential clock input.
Crystal oscillator interface. XTAL_IN is the input. XTAL_OUT is the output.
Power supply pin for VCXO charge pump.
NOTE:
Pullup and Pulldown
refer to internal input resistors. See Table 2,
Pin Characteristics,
for typical values.
Table 2. Pin Characteristics
Symbol
C
IN
R
PULLUP
R
PULLDOWN
Parameter
Input Capacitance
Input Pullup Resistor
Input Pulldown Resistor
Test Conditions
Minimum
Typical
4
51
51
Maximum
Units
pF
k
Ω
k
Ω
ICS813252DKI-02 REVISION A JANUARY 25, 2011
3
©2011 Integrated Device Technology, Inc.
ICS813252DI-02 Data Sheet
VCXO JITTER ATTENUATOR & FEMTOCLOCK
®
MULTIPLIER
Function Tables
Table 3A. Pre-Divider Selection Function Table
Inputs
PDSEL_2
0
0
0
0
1
1
1
1
PDSEL_1
0
0
1
1
0
0
1
1
PDSEL_0
0
1
0
1
0
1
0
1
÷P Value
1
193
256
2430
3125
9720
15625
19440 (default)
Table 3B. Output Divider Function Table
Inputs
ODxSEL_1
0
0
1
1
ODxSEL_0
0
1
0
1
÷Nx Value
25 (default)
5
4
2
NOTE: x denotes A or B.
ICS813252DKI-02 REVISION A JANUARY 25, 2011
4
©2011 Integrated Device Technology, Inc.
ICS813252DI-02 Data Sheet
VCXO JITTER ATTENUATOR & FEMTOCLOCK
®
MULTIPLIER
Table 3C. Frequency Function Table
Input
Frequency
(MHz)
0.008
0.008
0.008
0.008
1.544
1.544
1.544
1.544
2.048
2.048
2.048
2.048
19.44
19.44
19.44
19.44
25
25
25
25
77.76
77.76
77.76
77.76
125
125
125
125
155.52
155.52
155.52
155.52
VCXO
Frequency
(MHz)
25
25
25
25
25
25
25
25
25
25
25
25
25
25
25
25
25
25
25
25
25
25
25
25
25
25
25
25
25
25
25
25
FemtoClock
Feedback Divider
Value
25
25
25
25
25
25
25
25
25
25
25
25
25
25
25
25
25
25
25
25
25
25
25
25
25
25
25
25
25
25
25
25
FemtoClock
VCO Frequency
(MHz)
625
625
625
625
625
625
625
625
625
625
625
625
625
625
625
625
625
625
625
625
625
625
625
625
625
625
625
625
625
625
625
625
Output Frequency
(MHz)
25
125
156.25
312.5
25
125
156.25
312.5
25
125
156.25
312.5
25
125
156.25
312.5
25
125
156.25
312.5
25
125
156.25
312.5
25
125
156.25
312.5
25
125
156.25
312.5
÷P Value
1
1
1
1
193
193
193
193
256
256
256
256
2430
2430
2430
2430
3125
3125
3125
3125
9720
9720
9720
9720
15625
15625
15625
15625
19440
19440
19440
19440
÷Nx Value
25
5
4
2
25
5
4
2
25
5
4
2
25
5
4
2
25
5
4
2
25
5
4
2
25
5
4
2
25
5
4
2
NOTE: x denotes A or B.
ICS813252DKI-02 REVISION A JANUARY 25, 2011
5
©2011 Integrated Device Technology, Inc.
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