Junction Temperature Range . . . . . . . . . . . . . . . . -40
o
C to 150
o
C
CAUTION: Stresses above those listed in “Absolute Maximum Ratings” may cause permanent damage to the device. This is a stress only rating and operation
of the device at these or any other conditions above those indicated in the operational sections of this specification is not implied.
NOTES:
1.
θ
JA
is measured with the component mounted on an evaluation PC board in free air.
2. The MOSFET Output Drain is internally clamped with a Drain-to-Gate zener diode that turns on the MOSFET; holding the Drain at the
Output Clamp voltage VOC.
3. The output drive is protected by an internal current limit. The I
CL
over-current limiting threshold parameter specification defines the max-
imum current. The maximum current with all outputs ON may be further limited by dissipation.
4. Device dissipation is based on thermal resistance capability of the package in a normal operating environment. The junction to ambient
thermal resistance of 60
o
C/W is defined here as a PC Board mounted device with minimal copper. With approximately 2 square inches
of copper area as a heat sink, it is practical to achieve 35
o
C/W thermal resistance. Further reduction in the thermal resistance can be
achieved with additional PC Board Copper ground area or an external heat sink structure next to the ground leads at the center of the
package.
Electrical Specifications
PARAMETER
V
DD
= 4.5V to 5.5V, V
SS
= 0V, T
A
= -40
o
C to 125
o
C; Unless Otherwise Specified
SYMBOL
CONDITIONS
MIN
TYP
MAX
UNITS
OUTPUTS DRIVERS (DR0 TO DR7)
Output Channel Resistance
Over-Current Limiting Threshold
Output Clamping Voltage
Output Clamping Energy
Output OFF Leakage Current
Open-Load Fault Threshold
Output Rise Time
Output Fall Time
Turn-On Delay
Turn-Off Delay
POWER SUPPLY
Power On Reset Threshold
V
DD
Logic Supply Current
V
DD(POR)
I
DD
All Outputs ON or OFF
3.2
-
-
-
4.4
10
V
mA
r
DSON
I
CL
V
OC
E
OC
I
LK
R
OLD
t
R
t
F
t
ON
t
OFF
1ms Single Pulse Width, T
A
= 25
o
C,
(Refer to Figure 3 for SOA Limits).
V
OUT
= 14.5V
V
OUT
= 14.5V, Output Off
R
L
= 30Ω, V
OUT
= 14.5V
R
L
= 30Ω, V
OUT
= 14.5V
R
L
= 30Ω, V
OUT
= 14.5V
R
L
= 30Ω, V
OUT
= 14.5V
I
OUT
= 0.5A
-
1.5
40
-
-
4
1
1
-
-
-
-
50
85
-
-
-
-
-
-
0.8
3.5
60
-
180
200
12
12
12
12
Ω
A
V
mJ
µA
kΩ
µs
µs
µs
µs
LOGIC INPUTS (INx, SI, SCK, RST, CS)
High Level Input Voltage
Low Level Input Voltage
Input Hysteresis
High Output Voltage, SO, INT
Low Output Voltage, SO
Input Pull-Down Current, INx
Reset Input Pull-Up Current, RST
V
IH
V
IL
V
ILHYS
V
OL
V
OH
I
INPD
I
RPU
Current Sink = 1.6mA
Current Source = -0.8mA
0.7xV
DD
-
0.8
-
V
DD
-0.8
75
20
-
-
-
-
-
-
-
-
0.2xV
DD
-
0.4
-
250
120
V
V
V
V
V
µA
µA
2
HIP0060
Electrical Specifications
PARAMETER
DIAGNOSTIC
Pulse Width, INT
Fault Response Time
t
INT
t
FAULT
3
-
-
-
25
16
µs
µs
V
DD
= 4.5V to 5.5V, V
SS
= 0V, T
A
= -40
o
C to 125
o
C; Unless Otherwise Specified
(Continued)
SYMBOL
CONDITIONS
MIN
TYP
MAX
UNITS
OVER-TEMPERATURE PROTECTION
Over-Temperature Shutdown
T
SD
160
-
-
o
C
SERIAL PERIPHERAL INTERFACE TIMING
(Capacitance Each Pin, C
L
= 200pF)
SCK Period
SCK Clock High/Low Time
SCK Rise/Fall Time
Enable Lead/Lag Time
Output Data Valid Time
Data Setup Time
Disable Time
t
CYC
t
WSCKH,
t
WSCKL
t
rSCK
,
t
fSCK
t
LEAD
,
t
LAG
t
V
t
SU
t
DIS
500
200
-
250
-
-
-
-
-
-
-
-
-
-
-
-
30
-
170
30
250
ns
ns
ns
ns
ns
ns
ns
Description of Diagnostics
OC (Over-Current) Fault Mode
In a short circuit or over-current fault condition when an out-
put is switched on, the output current is limited to the I
CL
maximum as defined in the Electrical Specifications. An OC
fault condition does not shutdown the output. The current is
sensed and feedback is directed to the gate of the MOS Out-
put Driver. The gate voltage is reduced to maintained the
specified level of current limiting. In this mode, the drain volt-
age will increase and cause increased dissipation.
OT (Over-Temperature) Fault Mode
Under a high dissipation over-temperature fault condition,
the output temperature is detected and compared to a preset
threshold level. When the OT threshold is exceeded, thermal
shutdown for that output occurs. The Gate Control Latch
drive to the output is switched off and a status flag (the OT
Bit) for the fault is set. The output shutdown action is inde-
pendent of the IN input state. However, the Gate Control
Latch and OL Bit will be reset on the next rising edge of the IN
input and, if the fault still exists, the shutdown action will repeat.
Diagnostic action for an OT fault includes feedback of the
fault status to the Serial Diagnostic Register for a SPI bus
data output. Also, as shown in the Block Diagram, the OT
fault status bit information is ORed into a one-shot that
drives an open drain to provide an INT interrupt signal out-
put. The INT output has a specified timing from the one-shot
multi and is defined in the Electrical Specifications as t
INT
.
OL (Open-Load) Fault Mode
An open-load fault mode sequence consists of setting a sta-
tus flag (the OL Bit) when an output open load condition is
detected. If the output impedance is greater than a preset
threshold, as detected when the input is off; the status bit is
set. The OL Bit is reset on the next falling edge of the IN
input signal. The off-on detection sequence will repeat as
long as the output impedance is higher than the detection
threshold, as detected in the off state.
Diagnostic action for an OL fault mode differs from the OT
fault mode by not forcing an output shutdown through the
Gate Controlled Latch. Also, because the OL fault is
detected in the off state, the status flag is reset on the falling
edge of the input instead of the rising edge. The OL output
information to the Serial Diagnostic Register and the INT pin
is the same as the OT fault mode action.
ORed Fault Bits
It is important to note that the trigger input to the one-shot is
locked-out for the t
INT
duration and any fault that may have
occurred in the t
INT
window will not be displayed at the INT
output. However, all 8 fault bits may still be read as data from
the SO output when clock by the SCK input. The INT fault
output is provided as an interrupt signal to flag the immedi-
ate occurrence of a fault and take appropriate action as
defined by the microcontroller to the SPI bus and the users
programming. The INT fault output may be ORed with other
ICs to provide a system microcontroller interrupt to indicate
the presence of a fault.
3
HIP0060
Serial Diagnostic Link
A serial diagnostic link via the SPI bus provides the means
to clock fault data in and out of the fault register to the micro-
controller. When the microcontroller receives an INT inter-
rupt signal, data is clocked from the Serial Diagnostic
Register to determine what fault bit has been set. Appropri-
ate action for the fault may then be taken, as defined by the
programming of the microcontroller.
Serial Diagnostic Register
Fault bits consist of one OT bit and one OL bit for each
switching channel (A, B, C and D). Data is transferred out
of SO MSB first on the rising edge of SCK after CS goes
low. Data is shifted into the input shift register on the falling
edge of SCK. The defined order of the DO0 to DO7 fault
bits is as follows:
BIT
DO0
DO1
DO2
DO3
DO4
DO5
DO6
DO7
NAME
OTA
OTB
OTC
OTD
OLA
OLB
OLC
OLD
CONDITION REQUIRED TO SET BIT
OT in Output Driver A, T
J
≥
T
LIM
OT in Output Driver B, T
J
≥
T
LIM
OT in Output Driver C, T
J
≥
T
LIM
OT in Output Driver D, T
J
≥
T
LIM
OL in Output Driver A, OFF Load > R
OLD
OL in Output Driver B, OFF Load > R
OLD
OL in Output Driver C, OFF Load > R
OLD
OL in Output Driver D, OFF Load > R
OLD
HIP0060 devices may be linked in cascade for the purposes
of SPI control. Serial data is clocked in and out of each
HIP0060 and then back to the host microcontroller. All linked
devices have a common control sequence. When CS goes
low, fault data is shifted to the Serial Diagnostic Register.
SCK must be low when CS goes low. Also, when CS goes
low, SO changes from a three-state to a low state and
remains low until SCK goes high. Serial data is transferred
by SCK. After the serial data is transferred, SCK must
remain low as CS goes high. The serial data transfer must
be a continuous sequence while CS is low.
Serial Peripheral Interface
The Serial Peripheral Interface (SPI) bus is system con-
trolled by a host micro. The SPI bus controls the Serial Diag-
nostic Link with the CS (Chip Select), SCK, SI, SO and RST
(Reset) lines. Figures 4 and 5 define the timing and protocol
for the bus.
Reset Operation
The RST input is an active low reset input. When RST is low,
the internal diagnostic flags are cleared but not the shift reg-
ister. When RST is low, all outputs and output switches are
disabled. To clear the shift register, CS is switched from high
to low during or after a reset while there are no active faults,
jamming data from the cleared fault flags into the shift regis-
tor. The RST input has an internal pull-up to sustain a logic
high when floating.
The V
DD
input is the power supply to the 5V logic and the
POR function. When the V
DD
is less than the V
DD(POR)
threshold, the output drivers are shutoff. To insure that the
diagnostic link shift register is correct after V
DD
is less than
V
DD(POR)
, a manual reset must be executed.
4.7kΩ
INT
V
DD
+5V
OUTA
SOLENOID
RST
OUTB
INA
INB
INC
IND
HIP0060
OUTC
RELAY
V
BATT
LAMP
OUTD
M
MOTOR
V
BATT
FIGURE 1. TYPICAL HIP0060 APPLICATION AS A LOW SIDE SWITCH FOR INDUCTIVE LOADS, LAMPS AND SMALL LINEAR
MOTORS OR STEPPER MOTORS
4
HIP0060
+5V
4.7kΩ
RST
INA
OUTB
50Ω
5V, 100µs
2% DUTY CYCLE
FUNCTION GEN.
IND
INT
INB
INC
HIP0060
(TIMING TEST
CIRCUIT)
OUTC
30Ω
V
DD
+14.5V
30Ω
4.7kΩ
OUTA
30Ω
OUTD
GND
30Ω
5V
V
IN
3V
0V
t
ON
t
r
14.5V
V
OUT
0V
10%
10%
90%
1V
t
OFF
t
f
90%
FIGURE 2. INPUT TO OUTPUT SWITCHING TIME DIAGRAM FOR EACH SWITCHING CHANNEL. THE CONDITIONS SHOWN
REFER TO THE TIMING TEST CIRCUIT
10000
ENERGY (mJ)
1000
100
SAFE OPERATING AREA
BELOW LINE
10
0.1
1
TIME (ms)
10
100
FIGURE 3. MAXIMUM SINGLE PULSE ENERGY SAFE OPERATING AREA FOR EACH CLAMPED OUTPUT DRIVER, T
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