Preliminary
FM573/574
Nonvolatile Octal Latch/Register
Features
8-bit Nonvolatile Latch
•
Logic state is preserved in the absence of power
•
Over 10 Billion (10
10
) nonvolatile state changes
•
Advanced high-reliability ferroelectric process
Operates like conventional CMOS logic
•
Transparent (573) or D-Flip-flop (574) operation
•
FM573 transparent for C high, latched for C low
•
FM574 data is clocked on the rising edge of C
•
33/80 ns data propagation delay (5V/3V)
•
30 MHz/12 MHz Maximum frequency (5V/3V)
Automatic Nonvolatile Operation
•
Latched state is stored automatically
•
State is automatically restored on power-up
•
Power supply monitor prevents low-VDD writes
Low Power Operation
•
Supply voltage of 2.7V to 5.5V
•
125
µA
standby current
Industry Standard Configuration
•
Industrial temperature -40° C to +85° C
•
20-pin SOP or DIP
Description
The FM573 and FM574 are innovative circuits that
store inputs like conventional logic families, and then
retain the stored state in the absence of power. These
products solve three basic problems in an elegant
fashion. First, they provide continuous access to
nonvolatile system settings without performing a
memory read operation or using dedicated processor
I/O pins. Second, they allow the storage of signals or
data that may change frequently and possibly without
notice. Third, they allow the nonvolatile storage of a
few bits of data or system settings without the system
overhead and extra pins of a serial memory. The
FM573 is a transparent latch. The inputs are passed
to the outputs when the clock is high; the state is
latched when the clock goes low. The FM574 is a D-
type register. Inputs are stored and passed to the
outputs on the rising edge of the clock. The
nonvolatile latch is a unique product that serves a
variety of applications. A few ideas as follows:
ü
Controls relays and valves with automatic setting
on power-up without processor intervention.
ü
Interface to soft/momentary front-panel switches
and indicator lamps. Capture switch settings and
light LED’s without processor intervention.
ü
Replaces jumpers & control signal routing
ü
Initialize state of I/O card signals.
ü
Save system errors or status codes when power
fails with a fast, no overhead write and automatic
restore on power up.
ü
Eliminate the overhead of serial memory for
systems needing only a few bits of data.
The FM573 and FM574 are provided in a 20-pin DIP
or SOP. They are rated from –40C to +85C.
This data sheet contains specifications for a product under development.
Characterization is not complete; specifications may change without notice.
Pin Configuration
OE
D0
D1
D2
D3
D4
D5
D6
D7
VSS
1
2
3
4
5
6
7
8
9
10
20
19
18
17
16
15
14
13
12
11
VDD
Q0
Q1
Q2
Q3
Q4
Q5
Q6
Q7
C
Pin Names
D0-D7
Q0-Q7
C
/OE
VSS
VDD
Function
Data in
Data Out
Clock/Latch Enable
Output enable
Ground
Supply Voltage
Ordering Information
FM573-P
FM573-S
FM574-P
FM574-S
Transparent latch, 20-pin plastic DIP
Transparent latch, 20-pin SOP
Register, 20-pin plastic DIP
Register, 20-pin SOP
Other package types may be available. Contact
the factory for more information.
Ramtron International Corporation
1850 Ramtron Drive, Colorado Springs, CO 80921
(800) 545-FRAM, (719) 481-7000, Fax (719) 481-7058
27 March 2001
www.ramtron.com
1/10
Ramtron
Figure 1. Block Diagram
Mux
FM573/574
Dn
S
1
S
2
D
D
Q
Qn
OE
Q
Mux
C
S
1
S
2
D
Nonvolatile
section
Power-up Restore
State Change
Detect
Nonvolatile Latch
Q
D
L
VDD
Power
Monitor
Q
Reference
Pin Description
Pin Name
/OE
C
D0-D7
Q0-Q7
VSS
VDD
Pin Number
1
11
2-9
12-19
10
20
I/O
I
I
I
O
I
I
Pin Description
Output enable. When low, the outputs are driven. When high, the outputs
are tri-stated.
Controls the latching of data according to the truth tables below.
Data in.
Data out.
Ground
Supply Voltage
Functional Tables
FM573 Table
/OE
1
0
0
1
X
0
1
1
C
Dn
X
X
Dn
Dn
Internal
Qn
X
Qn
Dn
Dn
Output
Qn
Hi-Z
Qn
Dn
Hi-Z
Description
Tri-state outputs
Outputs enabled, hold state
Transparent
Load data, outputs tri-state
FM574 Table
/OE
1
0
0
1
X
X
↑
↑
C
Dn
X
X
Dn
Dn
Internal
Qn
X
Qn
Dn
Dn
Output
Qn
Hi-Z
Qn
Dn
Hi-Z
Description
Tri-state outputs
Outputs enabled, hold state
Load data, outputs enabled
Load data, outputs tri-state
27 March 2001
2/10
Ramtron
FM573/574
This power up sequence occurs as follows. On
detection of a power-up, the internal nonvolatile latch
is read. This value is then placed on an internal
version of the Dn input. A single internal clock is
generated to cause the user latch to accept the
restored data. After this process is comp lete, the latch
provides normal user-controlled operation. Users
should not attempt to latch externally supplied data
prior to t
PUH
after VDD reaches V
MIN
. The following
diagram illustrates the power-up and down
sequences.
Figure 2. Power Cycle Flow Chart
Overview
Nonvolatile logic is a revolutionary product family
that simplifies the design of system control functions.
The FM573 is a transparent octal latch; the FM574 is
an octal D-type register. These products are unique
because the stored values also are retained in the
absence of power. They are pin and functionally
compatible with their industry standard CMOS
equivalents. Any change in the latched state
automatically is written into a nonvolatile
ferroelectric latch. This function is possible due to the
fast write time and extremely high write endurance of
the underlying ferroelectric memory technology. A
new state becomes nonvolatile no more than 500 ns
(VDD=5V) after the write begins.
Users interface to a conventional latch rather than
directly to the nonvolatile latch. Equivalent
ferroelectric nonvolatile latches shadow the user’s
latches. They offer a very high but not unlimited
number of write-cycles. Therefore, the internal state
machine writes to the nonvolatile latch only if the
latched state has changed in order to minimize the
actual number of nonvolatile write-cycles. This
determination is made independently for each bit.
Due to the short write-time and realistic power slew
rates, it is virtually impossible for the system to lose
power before the nonvolatile state is acquired.
Power Down Sequence
An internal power monitor blocks updates to the
nonvolatile latch when VDD is below V (internal
MIN
voltage reference). The power supply monitor also
blocks write access to the user latch when VDD is
below V . To guarantee a proper nonvolatile write
MIN
of the last value, state changes should cease t
PDS
before VDD reaches V
MIN
. The V
MIN
threshold is low
enough that no special action may be needed in
systems with slow slew rates. For fast power supply
slew-rates or for systems that run down to relatively
low supply voltages, the user should employ some
form of low-VDD reset that trips above V
MIN
.
Power Up
The V
MIN
threshold is a critical parameter for several
aspects of product operations. On power-up, the
FM573/574 automatically restores the Qn outputs
(and internal latches) to the previously stored state.
This process begins as VDD rises to V
MIN
and is
completed t
RES
afterward. Thus for all practical
purposes, the nonvolatile values have been restored
as soon as the system logic is functional on power-
up. After the restore process, the latch is
indistinguishable from its last state prior to power
down and operates normally.
System VDD rises,
bandgap begins to function
No
No
VDD > VMIN?
VDD < VMIN
Yes
Yes
Read nonvolatile
store
Complete NV-
writes in progress
No
Block new writes to
NV-Latch, user latch
Read
complete?
Yes
Restore data to
user latch, drive
pins
No
Restore
complete?
Yes
Allow user access
to latch, normal
operation
27 March 2001
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Ramtron
FM573/574
power is lost, the nonvolatile shadow-latches retain
the last latched state.
On power up, the ferroelectric latches are read. The
outputs of these latches will be placed on the internal
Dn inputs. The power control circuit will then cause
the internal ‘C’ signal to go high. This rising edge
passes the nonvolatile value instead of the external
input into the user register. The internal Clock will
then be released and the nonvolatile value will be
stored into the user register. This entire restore
process takes t
RES
from VDD > V
MIN
. After the
restored nonvolatile value is loaded into the user
register, normal operation begins. The first user write
should occur t
PUH
after VDD > V
MIN
.
Functional Description - FM573
The FM573 is an octal transparent latch. The Qn
outputs track the Dn inputs while the Clock C signal
is logic 1. When the C signal goes to logic 0, the Dn
inputs are latched. In this aspect, the FM573 operates
identically to a conventional latch of the same type.
As shown above, it has the same functional truth
table as an ordinary 573-type product. The FM573 is
unique in its behavior during power up and power
down. It also is unique in providing behind the scenes
intelligence to manage the storage of settings.
Each latched state is compared to the stored
nonvolatile state. Comparison is made for each
individual bit. If any bit has changed from its stored
value, the new bit value automatically is written to
the corresponding nonvolatile ferroelectric latch.
Only the changed bits are written. For the transparent
version, unlatched changes on the Qn outputs are not
written to nonvolatile storage. This operation
continues as long as power is within tolerance (above
V
MIN
). The nonvolatile circuit operates entirely in the
background and has no operating impact. When
power is lost, the nonvolatile shadow-latches retain
the final latched state.
On power up, the ferroelectric latches are read. The
outputs of these latches will be placed on the internal
Dn inputs. The power control circuit will then cause
the internal ‘C’ signal to go high. Rather than passing
the inputs signal to the output in transparent fashion,
it will pass the nonvolatile value instead. After
satisfying the minimum high clock-time, the internal
Clock is released and the nonvolatile value is loaded
into the user latch. This entire restore process takes
t
RES
from V > V
MIN
. After the restored nonvolatile
DD
value is loaded into the user latch, normal operation
begins. The first user write should occur t
PUH
after
VDD > V
MIN
.
Applications
The FM573/FM574 runs at a speed that is
comparable to the industry standard HC family logic.
However, the nonvolatile-write operations, while fast
in nonvolatile memory terms, are slower. Therefore,
the nonvolatile logic runs ‘behind’ the user logic.
Three practical scenarios are identified in this data
sheet. One scenario that is not practical is to have
rapidly changing states, at high speed, continuing
indefinitely. For example, an address latch on a
microprocessor bus is not feasible due to limited
nonvolatile write endurance.
First, a free running clock in the kHz (or less) range
is applied to the FM574. In this application, the
nonvolatile logic can keep pace with state changes
and continue for relatively long periods to
indefinitely depending on the clock frequency. Slow
mechanisms such as relays and valves can be
controlled, and front panel interfaces can be made.
The second scenario is to employ an event driven
clock. The host issues one clock or a high-speed burst
as needed to an FM573 or FM574. In the case of a
high speed burst, the nonvolatile logic may get
behind, but will catch up when the burst is
completed. A special variation is to connect the clock
input to a power-down reset device. This circuit
captures a snapshot of the inputs on power-down. In
this application, care must be taken in the system
design to avoid capturing the inputs on power-up and
thereby losing the old setting. A clock that is either
software generated or controlled by other logic may
be used as well.
The third scenario is to monitor a continuous data
stream and to hold it when an event occurs. This is
analogous to a nonvolatile track-and-hold function.
For this case, the hold signal is applied to an FM573.
Diagrams of these applications are shown below.
Functional Description - FM574
The FM574 is an octal D
-register. Its behavior is
similar to the FM573 except that Qn outputs do not
change until the rising edge of the Clock. On the
rising edge of the clock signal, the inputs are loaded
and passed to the Qn outputs. In this aspect, the
FM574 operates identically to a conventional latch of
the same type.
The latched state is compared to the stored
nonvolatile state for each bit. If any bit has changed
from its stored value, the new value automatically is
written to the nonvolatile ferroelectric latch. This
operation continues as long as power is within
tolerance. The nonvolatile circuit operates entirely in
the background and has no operating impact. When
27 March 2001
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Ramtron
Figure 3. Applications
FM573/574
kHz Control & Monitoring
Power-fail & Watchdog Reset
Event Capture
a1
a2
a3
a4
a1
a2
a3
a4
VDD1 b1
b2
b3
b4
b1
b2
b3
b4
D
0
FM574
Q
0
Relay
Relay
FM574
D
0
Q
0
MCU
D
7
Q
7
GND
Microprocessor
Timer output
= 1 kHz
FM574
Q
0
D0
D
7
Q
7
RST
Dog
Selector
Q
7
D7
1
2
3
1232
PB
TD
TOL
8
VDD
ST
RST
RST
7
6
5
GND
4
FM574
Timing
VDD
4.5V
2.5V
2.0V
4.5V
2.5V
2.0V
RST
Nonvolatile Track & Hold
Joystick
A/D
A
1
A
2
A
3
A
4
DAC
1
DAC
2
D0-7
3
D
0
FM573
Q
0
8
D
7
Q
7
To
Controller
Hold
This figure is a conceptual illustration of different modes of operation, not a complete circuit design.
27 March 2001
5/10
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