www.fairchildsemi.com
FMS72510
Phase Locked Loop Clock Driver
Features
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PC-133 Spread Spectrum Compliant
Frequency Range of 25 to 140 MHz
V
DD
Range of 3.0 to 3.6 Volts
Up to 11 outputs
Less than 100 pS of Output to Output Skew
Less than 90 pS of Cycle to Cycle Jitter
Output Enable pin
Integrated Damping Resistor
Commercial Temperature Range
Available in 24 pin TSSOP
Description
FMS72510 is a zero delay clock buffer designed for high fan
out applications. It contains 11 outputs. It provides precise
phase and frequency alignment between incoming clock and
the output clocks. This makes it ideal for high speed applica-
tion in the range of 25 to 140 MHz. The Phase Locked Loop
is capable of tracking incoming clock modulation of up to
±1% of the clock period. With the exception of FBOUT, the
output Enable (OE) pin, when pulled low, will force the out-
puts to logic low.
Block Diagram
FB O U T
Q0
Q1
Q2
Q3
FBIN
PLL
CLKIN
Control
Logic
Q4
Q5
Q6
Q7
Q8
Q9
OE
REV. 1.0 8/11/00
PRODUCT SPECIFICATION
FMS72510
Pin Assignments
24 TSSO P
AGND
V
DD
Q0
Q1
Q2
GND
GND
Q3
Q4
V
DD
OE
FBOUT
1
2
3
4
5
6
7
8
9
10
11
12
FMS72510
24
23
22
21
20
19
18
17
16
15
14
13
CLKIN
AV
DD
V
DD
Q9
Q8
GND
GND
Q7
Q6
Q5
V
DD
FB I N
Pin Description
Pin Name
GND
AGND
V
DD
AV
DD
Q (0:9)
OE
FBOUT
FBIN
CLKIN
Pin #
6, 7, 18, 19
1
2, 10, 14, 22
23
3, 4, 5, 8, 9, 15,
16, 17, 20, 21
11
12
13
24
Pin Type
PWR
PWR
PWR
PWR
OUT
IN
OUT
IN
IN
Pin Function Description
Ground Connection:
Connect all ground pins to the common system
ground plane.
Analog Ground Connection:
Connect to common system ground plane.
Power Connection:
Power supply for all the outputs.
Power Connection:
Power supply for the PLL. When connected low, it
shuts off and bypass’s the PLL.
Clock outputs:
Outputs are buffer clocks of input.
Outputs Enable:
When low, all outputs, with the exception of FBOUT,
goes to logic low. Normal operation when asserted high.
Feedback Clock Output:
Dedicated pin for FB pin. It is not effected by
OE pin.
Feedback Clock Input:
PLL feedback input. The user connects it to
FBOUT.
Input Clock:
One of the inputs of the PLL.
Functionality Table
AVDD
L
L
H
H
OE
L
H
L
H
PLL
BYPASS
BYPASS
Enabled
Enabled
Q (0:9)
L
Buffered Clocked
L
Running in phase with CLKIN
FBOUT
Buffered CLKIN
Buffered CLKIN
Running in phase with CLKIN
Running in phase with CLKIN
2
REV. 1.0 8/11/00
FMS72510
PRODUCT SPECIFICATION
Absolute Maximum Rating
Symbol
V
DD
, V
IN
T
STG
T
B
T
A
Storage Temperature
Ambient Temperature
Operating Temperature
Parameter
Voltage on any pin with respect to ground
Ratings
–0.5 to 7.0
–65 to 150
–55 to 125
0 to 70
Units
V
°C
°C
°C
Stresses greater than those listed in the table may cause permanent damage to the device. These represent a stress rating only.
Operation of the device at these or any other conditions above those specified in the operating sections of this specification is
not implied. Maximum conditions for extended periods may effect reliability.
DC Electrical Characteristics
T
A
= 0 to 70°C; Supply Voltage V
DD
= 3.3 V ±0.3V, C
L
= 12pF (unless otherwise stated)
Parameter
Input Low Voltage
Input High Voltage
Input Low Current
Input High Current
High Output Voltage
Low Output Voltage
Input Capacitance
(1)
Supply Current
Clock Stabilization
(1)
Symbol
V
IL
V
IH
I
IL
I
IH
V
OH
V
OL
C
IN
I
DD
T
STAB
V
IN
= 0
V
IN
= V
DD
I
OH
= -6mA
I
OL
= 15mA
Frequency = 10MHz
Frequency = 100 MHz; C
L
= 12pF
Frequency = 133 MHz; C
L
= 12pF
From V
DD
= 3.3 V to 1% Target
NOTE:
1. Guaranteed by design, not subject to 100% production testing.
Conditions
Min.
GND – 0.3
2.0
-10
-10
2.4
2.5
Typ.
Max.
0.8
V
DD
+ 0.3
10
10
Units
V
V
µA
µA
V
V
pF
mA
mA
mS
3.1
0.5
200
230
0.8
6.0
290
320
1
AC Electrical Characteristics
T
A
= 0 to 70°C; Supply Voltage V
DD
= 3.3V ±0.3V, C
L
= 12 pF (unless otherwise stated)
Parameter
Clock Input Duty Cycle
Rise Time
(1)
Fall Time
(1)
Duty Cycle
(1)
Jitter (Cycle-Cycle)
(1)
Spread Spectrum Induced Skew
(1)
Output to Output Skew
(1)
Input to Output Delay
(1,2)
(1)
Symbol
D
T_IN
F
IN
T
R
T
F
D
T
T
JIT
T
SK_SSC
T
SK1
T
SK2
Conditions
AVDD = 3.3V
0.4 to 2.0V
2.0 to 0.4V
V
TH
= 1.25V
V
TH
= 1.25V; 100 & 133 MHz
V
TH
= V
DD
/2
V
TH
= V
DD
/2
C
LFB
= 4 pF; 100 & 133 MHz
Min.
40
25
–
–
45
-120
-200
-120
-100
Typ.
Max.
60
140
2.0
2.0
55
120
200
120
100
Units
%
MHz
nS
nS
%
pS
pS
pS
pS
Input Frequency Range
(1)
NOTE:
1. Guaranteed by design, not subject to 100% production testing.
2. Feedback trace length of 0.7”.
REV. 1.0 8/11/00
3
PRODUCT SPECIFICATION
FMS72510
Parameter Measurement Information
Duty Cycle Timing (D
T
)
t
1
t
2
D
T
=
1.5V
1.5V
1.5V
t
2
t
1
x 100
Rise/Fall Time (T
R
/T
F
)
2.0V
0.4V
OUTPUT
2.0V
0.4V
0V
3.3V
T
R
T
F
Output to Output Skew (T
SK1
)
1.5V
Q
0
1.5V
Any Output
T
SK1
Input to Output Delay (T
SK2
)
1.5V
CLKIN
1.5V
FBIN
T
SK2
4
REV. 1.0 8/11/00
FMS72510
PRODUCT SPECIFICATION
Application Diagram
CLKIN
IN
Q
0
PLL
Q
N
FBIN
C
FBOUT
Note:
Feedback capacitor value 'C' is to be determined
based on the phase characteristics of the PLL.
REV. 1.0 8/11/00
5
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