CXA3562AR
LCD Driver
Description
The CXA3562AR is a driver IC developed for use
with Sony polycrystalline silicon TFT LCD panels. It
supports digital 2-parallel and single input, and the
input data is analog demultiplexed into 12 phases and
output. The CXA3562AR can directly drive an LCD
panel, and the VCOM setting circuit and precharge
pulse waveform generator are also on-chip.
Features
•
Supports 10-bit 2-parallel and single input
•
Supports signals up to UXGA
(1/2 clock when using UXGA signals)
•
Low output deviation by on-chip output offset cancel circuit
•
•
•
•
Supports both line inversion and dot and line inversion
On-chip timing generator with ECL
VCOM voltage generation circuit
Precharge pulse waveform generation circuit
100 pin LQFP (Plastic)
Applications
LCD projectors and other video equipment
Absolute Maximum Ratings
(V
SS
= 0V)
•
Supply voltage
V
CC
16
V
V
DD
5.5
V
•
Operating temperature
Topr
–20 to +70
°C
•
Storage temperature
Tstg –65 to +150 °C
•
Allowable power dissipation P
D
2000
mW
Recommended Operating Conditions
•
Supply voltage
V
CC
15.0 to 15.5
V
DD
4.75 to 5.25
•
Operating temperature
Topr
–20 to +70
V
V
°C
Sony reserves the right to change products and specifications without prior notice. This information does not convey any license by
any implication or otherwise under any patents or other right. Application circuits shown, if any, are typical examples illustrating the
operation of the devices. Sony cannot assume responsibility for any problems arising out of the use of these circuits.
–1–
E01820A22
CXA3562AR
Block Diagram and Pin Configuration
VCOM_OFST
VCOM_OUT
SID_OUTX
75 74 73 72 71 70 69 68 67 66 65 64 63 62 61 60 59 58 57 56 55 54 53 52 51
D_A9 76
D_A8 77
D_A7 78
D_A6 79
D_A5 80
D_A4 81
D_A3 82
D_A2 83
D_A1 84
D_A0 85
GND 86
GND 87
GND 88
GND 89
GND 90
D_B9 91
D_B8 92
D_B7 93
D_B6 94
D_B5 95
D_B4 96
D_B3 97
D_B2 98
D_B1 99
D_B0 100
CAL_PLS
Offset Cancel Level Gen.
TG
FRP_OD
FRP_EV
D/A
S/H
S/H
S/H
S/H
S/H
S/H
S/H
S/H
S/H
S/H
S/H
S/H
S/H
S/H
S/H
S/H
S/H
S/H
S/H
S/H
S/H
D/A
S/H
S/H
S/H
S/H
S/H
S/H
S/H
S/H
S/H
S/H
S/H
S/H
S/H
S/H
S/H
SID Gen.
Vref Gen.
Line Inv.
Offset Cancel
Line Inv.
Offset Cancel
Line Inv.
Offset Cancel
Line Inv.
Offset Cancel
Line Inv.
Offset Cancel
Line Inv.
Offset Cancel
Line Inv.
Offset Cancel
Line Inv.
Offset Cancel
Line Inv.
Offset Cancel
Line Inv.
Offset Cancel
Line Inv.
Offset Cancel
Line Inv.
Offset Cancel
VCOM Gen.
SH_OUT1
SID_OUT
F/H_CNT
VREF_O
SL_SCN
PRG_LV
SL_DAT
VREF_I
SL_INV
SID_LV
TEST
DIRC
GND
GND
GND
GND
GND
PRG
V
DD
V
CC
NC
PS
50 PV
CC
49 SH_OUT2
48 NC
47 SH_OUT3
46 NC
45 SH_OUT4
44 NC
43 SH_OUT5
42 NC
41 SH_OUT6
40 GND
39 GND
38 PGND
37 GND
36 GND
35 SH_OUT7
34 NC
33 SH_OUT8
32 NC
31 SH_OUT9
30 NC
29 SH_OUT10
28 NC
27 SH_OUT11
26 PV
CC
1
TEST
2
MCLK
3
MCLKX
4
FRP
5
SHST
6
POSCTR0
7
POSCTR1
8
POSCTR2
9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25
CAL_IH
CAL_IL
GND
GND
GND
GND
GND
SHTEST
SIG.C
CAL_OL
POSCTR3
CAL_OH
GND
NC
DCFBOFF
SH_OUT12
SIG_OFST
–2–
CXA3562AR
Pin Description
Pin
No.
Symbol
I/O
Standard
voltage level
V
DD
Equivalent circuit
Description
2
3
MCLK
MCLKX
I
PECL
differential
(amplitude
0.4V or more
between
V
DD
to 2V)
or TTL input
140k
1k
2
1k
3
60k
GND
8k
140k
100µ
60k
Dot clock input.
PECL differential input or TTL
input. For TTL input, input to
MCLK and connect MCLKX to
GND through a capacitor.
V
DD
50k
4
FRP
I
High:
≥2.0V
Low:
≤0.8V
192
4
LCD panel AC drive inversion
timing input.
High: inverted
Low: non-inverted
See the Timing Chart.
GND
V
DD
50k
192
5
5
SHST
I
High:
≥2.0V
Low:
≤0.8V
GND
Internal sample-and-hold timing
circuit reset pulse input.
This pin is also used as the
offset cancel level insertion
timing input.
A reset is applied to the internal
timing generator at the falling
edge.
Output phase adjustment.
The output phase is adjusted in
MCLK period units when
SL_DAT (Pin 72) is high, and in
1/2 MCLK period units when
SL_DAT is low.
V
DD
6
7
8
9
POSCTR0
POSCTR1
POSCTR2
POSCTR3
50k
I
High:
≥2.0V
Low:
≤0.8V
192
6
7
8
9
GND
V
DD
30k
V
CC
20µ
16
SIG.C
I
1 to 5.0V
16
Signal center voltage (inversion
folded voltage) adjustment input.
The SH_OUT output center
voltage can be adjusted in the
range from 7.0 to 8.0V.
GND
V
DD
30k
V
CC
10µ
17
SIG_OFST
I
0 to 5.0V
17
GND
Output signal offset adjustment
from signal center voltage.
The SH_OUT output 100%
white level (at 3FF input) voltage
can be adjusted in the range
from 0 to 1V from the center
voltage.
–3–
CXA3562AR
Pin
No.
Symbol
I/O
Standard
voltage level
Equivalent circuit
V
CC
40µ
1k
145
18
19
GND
Description
18
19
CAL_OL
CAL_OH
O
3.0 to 6.0V
9.0 to 12.0V
Level output for canceling the
offset between channels.
Connect directly to CAL_IL and
CAL_IH, respectively.
V
CC
20k
21
22
CAL_IH
CAL_IL
O
9.0 to 12.0V
3.0 to 6.0V
30k
21
22
GND
V
DD
24k
24k
145
24
20µ
Level input for canceling the
offset between channels.
Connect directly to CAL_OL and
CAL_OH, respectively. When
using two CXA3562R, connect
the CAL_IL and CAL_IH of both
chips to the CAL_OL and
CAL_OH of only one CXA3562R.
Offset cancel function off.
Normally connect to GND to
use with the offset cancel
function on.
High (offset cancel function off)
when open.
24
DCFBOFF
I
GND
GND
PV
CC
25 27
25,
29,
33,
41,
45,
49,
27,
31,
SH_OUT12
35,
to
43,
SH_OUT1
47,
51
300
29 31
33 35
41 43
45 47
49 51
O
1.5 to 13.5V
300
Demultiplexed output of AC
inverse driven video signals.
Can be connected directly to
the LCD panel.
GND
V
CC
80µ
100k
500 145
53
500
53
VCOM_OUT
O
5.0 to 8.0V
LCD panel common voltage
output.
Can be set in the range from
the SH_OUT center potential
Vsig.c to Vsig.c – 2V by
VCOM_OFST.
GND
V
DD
2k
V
CC
80µ
54
VCOM_OFST
I
0 to 5.0V
54
100
GND
LCD panel common voltage
adjustment.
VCOM_OUT can be set in the
range from the SH_OUT center
potential Vsig.c to Vsig.c – 2V
by inputting 0 to 5V.
–4–
CXA3562AR
Pin
No.
Symbol
I/O
Standard
voltage level
V
CC
Equivalent circuit
Description
Precharge waveform output.
SID_OUTX outputs the inverse
of SID_OUT based on the
output center voltage. These
pins cannot directly drive the
LCD panel, so input to the LCD
panel with an external a buffer.
V
CC
100k
0.2p
145
56
100k
0.2p
GND
57
56
57
SID_OUTX
SID_OUT
O
1.5 to 13.5V
V
DD
29µ
58
59
PRG_LV
SID_LV
I
1.0 to 5.0V
50k
58
50k
59
GND
Precharge level setting.
Adjusts the SID_OUT and
SID_OUTX output potential.
PRG_LV is reflected when the
PRG input pin (Pin 60) is high,
and SID_LV is reflected when
PRG is low.
V
DD
100k
V
CC
10k
60
PRG
I
High:
≥2.0V
Low:
≤0.8V
60
50µ
GND
Timing pulse input for switching
the Pins 56 and 57 output levels.
(See PRG_LV (Pin 58) and
SID_LV (Pin 59).)
V
DD
70µ
10µ
68
VREF_I
I
3.2V
68
1k
280µ
GND
33.3k
Internal D/A converter reference
voltage input.
Normally connect directly to
VREF_O.
V
DD
2k
69
VREF_O
O
3.2V
20µ
20k
12.4k
GND
69
Reference voltage output.
Normally connect directly to
VREF_I, and connect to GND
through a 0.5 to 1.0µF capacitor.
V
DD
50k
70
F/H_CNT
I
High:
≥2.0V
Low:
≤0.8V
Open: Low
192
70
200k
GND
SH_OUT output timing selection.
High: SH_OUT1 to SH_OUT6
and SH_OUT7 to SH_OUT12
are output at different timing.
Low: SH_OUT1 to SH_OUT12
are output at the same timing.
–5–
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