INTEGRATED CIRCUITS
GTLPH16612
18-bit GTLP to LVTTL/TTL bidirectional
universal translator (3-State)
Product data
File under Integrated Ciruits ICL03
2001 Sep 28
Philips
Semiconductors
Philips Semiconductors
Product data
18-bit GTLP to LVTTL/TTL bidirectional
universal translator (3-State)
GTLPH16612
FEATURES
•
18-bit bidirectional bus interface
•
Translates between GTLP logic levels (B ports) and LVTTL/TTL
•
Edge rate control circuitry on the Bn outputs rising/falling edges to
•
5 V I/O tolerant on the LVTTL side
•
No bus current loading when LVTTL output is tied to 5 V bus
•
3-State buffers
•
Output capability: +64 mA/-32 mA on the LVTTL side; +40 mA on
•
LVTTL input levels on control pins
•
Power-up reset
•
Power-up 3-State
•
Positive edge triggered clock inputs
•
Latch-up protection exceeds 500 mA per JESD78
•
ESD protection exceeds 2000 V HBM per JESD22-A114,
200 V MM per JESD22-A115 and 750 V (Bn I/O exceeds 1000 V)
CDM per JESD22-C101
the GTLP side
minimize system noise in a multipoint backplane environment
logic levels (A ports)
DESCRIPTION
The GTLPH16612 is a high-performance BiCMOS product designed
for V
CC
operation at 3.3V with I/O compatibility up to 5 V.
The GTLPH16612 is unique in that pin 50 is a no connect and this
device can be used as a replacement device in sockets where
pin 50 is 3.3/5 V V
CC
or 3.3 V BIAS V
CC
.
This device is an 18-bit universal transceiver featuring non-inverting
3-State bus compatible outputs in both send and receive directions.
Data flow in each direction is controlled by output enable (OEAB and
OEBA), latch enable (LEAB and LEBA), and clock (CPAB and
CPBA) inputs. For A-to-B data flow, the device operates in the
transparent mode when LEAB is High. When LEAB is Low, the A
data is latched if CPAB is held at a High or Low logic level. If LEAB
is Low, the A-bus data is stored in the latch/flip-flop on the
Low-to-High transition of CPAB. When OEAB is Low, the outputs are
active. When OEAB is High, the outputs are in the high-impedance
state. The clocks can be controlled with the clock-enable inputs
(CEBA/CEAB).
Data flow for B-to-A is similar to that of A-to-B but uses OEBA,
LEBA and CPBA.
QUICK REFERENCE DATA
SYMBOL
t
PLH
t
PHL
C
IN
C
I/O
C
I/O
I
CCZ
PARAMETER
Propagation delay
An to Bn or Bn to An
Input capacitance (Control pins)
An I/O pin capacitance
Bn I/O pin capacitance
Total supply current
C
L
= 50 pF
V
I
= 0 V or V
CC
V
I/O
= 0 V or V
CC
V
I/O
= 0 V or 1.5 V
Outputs disabled
CONDITIONS
T
amb
= 25
°C
TYPICAL
UNIT
3.3 V
1.9
4
9
5.3
12
ns
pF
pF
pF
mA
ORDERING INFORMATION
PACKAGES
56-Pin Plastic SSOP
56-Pin Plastic TSSOP
TEMPERATURE RANGE
–40 to +85
°C
–40 to +85
°C
ORDER CODE
GTLPH16612DL
GTLPH16612DGG
DWG NUMBER
SOT371-1
SOT364-1
NOTE:
1. Standard packing quantities and other packaging data is available at
www.philipslogic.com/support/packages.
2001 Sep 28
2
853–2285 27174
Philips Semiconductors
Product data
18-bit GTLP to LVTTL/TTL bidirectional universal
translator (3-State)
GTLPH16612
PIN CONFIGURATION
OEAB
LEAB
A0
GND
A1
A2
V
CC
A3
A4
A5
GND
A6
A7
A8
A9
A10
A11
GND
A12
A13
A14
V
CC
A15
A16
GND
A17
OEBA
LEBA
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
56
55
54
53
52
51
50
49
48
47
46
45
44
43
42
41
40
39
38
37
36
35
34
33
32
31
30
29
CEAB
CPAB
B0
GND
B1
B2
NC
B3
B4
B5
GND
B6
B7
B8
B9
B10
B11
GND
B12
B13
B14
V
REF
B15
B16
GND
B17
CPBA
CEBA
PIN DESCRIPTION
PIN NUMBER
1, 27
29, 56
2, 28
55, 30
3, 5, 6, 8, 9, 10,
12, 13, 14, 15,
16, 17, 19, 20,
21, 23, 24, 26
54, 52, 51, 49,
48, 47, 45, 44,
43, 42, 41, 40,
38, 37, 36, 34,
33, 31
4, 11, 18, 25, 32,
39, 46, 53
7, 22
35
50
SYMBOL
OEAB/OEBA
CEBA/CEAB
LEAB/LEBA
CPAB/CPBA
NAME AND FUNCTION
A-to-B/ B-to-A Output
enable input (active Low)
B-to-A/A-to-B clock
enable
A-to-B/B-to-A Latch
enable input
A-to-B/B-to-A Clock input
(active rising edge)
Data inputs/outputs
(A side)
A0-A17
B0-B17
Data inputs/outputs
(B side)
GND
V
CC
V
REF
NC
Ground (0V)
Positive supply voltage
GTLP reference voltage
No connect
SW00486
2001 Sep 28
3
Philips Semiconductors
Product data
18-bit GTLP to LVTTL/TTL bidirectional universal
translator (3-State)
GTLPH16612
FUNCTION TABLE
INPUTS
CEAB
X
L
L
X
X
L
L
H
X=
H=
L=
↑
=
Z=
†=
OEAB
H
L
L
L
L
L
L
L
LEAB
X
L
L
H
H
L
L
L
CPAB
X
↑
↑
X
X
H
L
X
A
X
L
H
L
H
X
X
X
OUTPUT
B
Z
L
H
L
H
B
O
B
O§
B
O
Trans arent
Transparent
Clocked storage of A data
MODE
Isolation
Latched storage of A data
Clock inhibit
Don’t care
High voltage level
Low voltage level
Low to High
High impedance “off ” state
A-to-B data flow is shown: B-to-A flow is similar but uses OEBA, LEBA, CPBA, and CEBA. The condition when OEAB and OEBA are both
low at the same time is not recommended.
= Output level before the indicated steady-state input conditions were established.
§ = Output level before the indicated steady-state input conditions were established, provided that CPAB was Low before LEAB went Low.
LOGIC SYMBOL (Positive Logic)
V
REF
35
OEAB
1
CEAB
56
CPAB
55
LEAB
2
LEBA
28
CPBA
30
CEBA
29
OEBA
27
CE
A0
3
1D
C1
CLK
CE
1D
C1
CLK
54
B0
To 17 other channels
SW00894
2001 Sep 28
4
Philips Semiconductors
Product data
18-bit GTLP to LVTTL/TTL bidirectional universal
translator (3-State)
GTLPH16612
ABSOLUTE MAXIMUM RATINGS
1, 2
SYMBOL
V
CC
I
IK
V
I
I
OK
V
O
OUT
I
O
OL
I
OH
T
stg
PARAMETER
DC supply voltage
DC input diode current
DC input voltage
3
DC output diode current
DC output voltage
3
Current into any output in the LOW state
Current into any output in the HIGH state
Storage temperature range
V
I
< 0 V
A port
B port
V
O
< 0 V; A port
Output in Off or High state; A port
Output in Off or High state; B port
A port
B port
A port
CONDITIONS
RATING
–0.5 to +4.6
–50
–0.5 to +7.0
–0.5 to +4.6
–50
–0.5 to +7.0
–0.5 to +4.6
128
80
–64
–65 to +150
UNIT
V
mA
V
mA
V
V
mA
mA
mA
°C
NOTES:
1. Stresses beyond those listed may cause permanent damage to the device. These are stress ratings only and functional operation of the
device at these or any other conditions beyond those indicated under “recommended operating conditions” is not implied. Exposure to
absolute-maximum-rated conditions for extended periods may affect device reliability.
2. The performance capability of a high-performance integrated circuit in conjunction with its thermal environment can create junction
temperatures which are detrimental to reliability. The maximum junction temperature of this integrated circuit should not exceed 150
°C.
3. The input and output negative voltage ratings may be exceeded if the input and output clamp current ratings are observed.
RECOMMENDED OPERATING CONDITIONS
1, 2
SYMBOL
V
CC
V
TT
V
REF
V
I
V
IH
V
IL
I
OH
I
OL
∆t/∆v
∆t/∆V
CC
T
amb
PARAMETER
DC supply voltage
Termination voltage
GTL reference voltage
Input voltage
HIGH-level
HIGH level input voltage
LOW-level
LOW level input voltage
HIGH-level output current
LOW-level output current
Input transition rise or fall rate
Power-up rate
Operating free-air temperature range
GTL
GTLP
GTL
GTLP
B port
Except B port
B port
Except B port
B port
Except A port
A port
B port, GTL
B port, GTLP
A port
Outputs enabled
TEST CONDITIONS
3.3V RANGE LIMITS
MIN
3.0
1.14
1.35
0.74
0.9
0
0
V
REF
+50mV
2.0
—
—
—
—
—
—
—
20
–40
TYP
3.3
1.2
1.5
0.8
1
V
TT
V
CC
—
—
—
—
—
—
—
—
—
—
—
MAX
3.6
1.26
1.65
0.87
1.10
Note 3
5.5
—
—
V
REF
–50mV
0.8
–32
32
40
64
10
—
+85
UNIT
V
V
V
V
V
V
mA
mA
mA
mA
ns/V
µs/V
°C
NOTES:
1. Normal connection sequence is GND first; V
CC
, I/O, control inputs, V
TT
and V
REF
(any order) last.
2. V
REF
can be adjusted to optimize noise margins, but normally is two-thirds V
TT
.
3. V
TT
and R
TT
can be adjusted to accommodate backplane impedances if the DC recommended I
OL
ratings are not exceeded and the
absolute max V
I
rating is not exceeded.
2001 Sep 28
5
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