Direct Rambus
™
RIMM
™
Module
256 MBytes (128M x 16/18) based on 8Mx16/18
Overview
The Direct Rambus™ RIMM™ module is a general purpose
high-performance memory subsystem suitable for use in a
broad range of applications including computer memory,
personal computers, workstations, and other applications
where high bandwidth and low latency are required.
The 256MB Direct Rambus RIMM module consists of
sixteen 128M Direct Rambus DRAM (Direct RDRAM™ )
devices. These are extremely high-speed CMOS DRAMs
organized as 8M words by 16 or 18 bits. The use of Rambus
Signaling Level (RSL) technology permits 600MHz or
800MHz transfer rates while using conventional system and
board design technologies. Direct RDRAM devices are
capable of sustained data transfers at 1.25 ns per two bytes
(10ns per sixteen bytes).
The architecture of the Direct RDRAM allows the highest
sustained bandwidth for multiple, simultaneous randomly
addressed memory transactions. The separate control and
data buses with independent row and column control yield
over 95% bus efficiency. The Direct RDRAM's thirty-two
banks support up to four simultaneous transactions.
Key Timing Parameters/Part Numbers
The following table lists the frequency and latency bins
available from RIMM modules. An optional -LP designator
is used to indicate low power modules.
Organization
128M x 16
128M x 16
128M x 16
128M x 18
128M x 18
128M x 18
I/O Freq. t
rac
(Row Access
MHz
Time) ns
600
800
800
600
800
800
53
45
40
53
45
40
Part Number
HYMR116128-653
HYMR116128-845
HYMR116128-840
HYMR118128-653
HYMR118128-845
HYMR118128-840
Form Factor
The Direct Rambus RIMM modules are offered in a 184-pin
1mm pin pitch form factor suitable for desktop and other
system applications.
Features
184-pin 1mm pin spacing
Card Size: 133.35mm x 31.75mm x 1.27mm
(5.25” x 1.25” x 0.050”)
256MB Direct RDRAM storage
Each RDRAM has 32banks, for 512 banks total on
module
Gold plated contacts
RDRAMs use Chip Scale Package (CSP)
Serial Presence Detect support
Operates from a 2.5 volt supply (±5%)
Low power and powerdown self refresh modes
Separate Row and Column buses for higher efficiency
Rev. 0.0 /Feb. 99
1
Preliminary
HYMR11696/11896 Series
Pinouts and Pin Names
Pin
A1
A2
A3
A4
A5
A6
A7
A8
A9
A10
A11
A12
A13
A14
A15
A16
A17
A18
A19
A20
A21
A22
A23
A24
A25
A26
A27
A28
A29
A30
A31
A32
A33
A34
A35
A36
A37
A38
A39
A40
A41
A42
A43
A44
A45
A46
Pin Name
Gnd
LDQA8
Gnd
LDQA6
Gnd
LDQA4
Gnd
LDQA2
Gnd
LDQA0
Gnd
LCTMN
Gnd
LCTM
Gnd
NC
Gnd
LROW1
Gnd
LCOL4
Gnd
LCOL2
Gnd
LCOL0
Gnd
LDQB1
Gnd
LDQB3
Gnd
LDQB5
Gnd
LDQB7
Gnd
LSCK
Vcmos
SOUT
Vcmos
NC
Gnd
NC
Vdd
Vdd
NC
NC
NC
NC
Pin
B1
B2
B3
B4
B5
B6
B7
B8
B9
B10
B11
B12
B13
B14
B15
B16
B17
B18
B19
B20
B21
B22
B23
B24
B25
B26
B27
B28
B29
B30
B31
B32
B33
B34
B35
B36
B37
B38
B39
B40
B41
B42
B43
B44
B45
B46
Pin Name
Gnd
LDQA7
Gnd
LDQA5
Gnd
LDQA3
Gnd
LDQA1
Gnd
LCFM
Gnd
LCFMN
Gnd
NC
Gnd
LROW2
Gnd
LROW0
Gnd
LCOL3
Gnd
LCOL1
Gnd
LDQB0
Gnd
LDQB2
Gnd
LDQB4
Gnd
LDQB6
Gnd
LDQB8
Gnd
LCMD
Vcmos
SIN
Vcmos
NC
Gnd
NC
Vdd
Vdd
NC
NC
NC
NC
Pin
A47
A48
A49
A50
A51
A52
A53
A54
A55
A56
A57
A58
A59
A60
A61
A62
A63
A64
A65
A66
A67
A68
A69
A70
A71
A72
A73
A74
A75
A76
A77
A78
A79
A80
A81
A82
A83
A84
A85
A86
A87
A88
A89
A90
A91
A92
Pin Name
NC
NC
NC
NC
Vref
Gnd
SCL
Vdd
SDA
SVdd
SWP
Vdd
RSCK
Gnd
RDQB7
Gnd
RDQB5
Gnd
RDQB3
Gnd
RDQB1
Gnd
RCOL0
Gnd
RCOL2
Gnd
RCOL4
Gnd
RROW1
Gnd
NC
Gnd
RCTM
Gnd
RCTMN
Gnd
RDQA0
Gnd
RDQA2
Gnd
RDQA4
Gnd
RDQA6
Gnd
RDQA8
Gnd
Pin
B47
B48
B49
B50
B51
B52
B53
B54
B55
B56
B57
B58
B59
B60
B61
B62
B63
B64
B65
B66
B67
B68
B69
B70
B71
B72
B73
B74
B75
B76
B77
B78
B79
B80
B81
B82
B83
B84
B85
B86
B87
B88
B89
B90
B91
B92
Pin Name
NC
NC
NC
NC
Vref
Gnd
SA0
Vdd
SA1
SVdd
SA2
Vdd
RCMD
Gnd
RDQB8
Gnd
RDQB6
Gnd
RDQB4
Gnd
RDQB2
Gnd
RDQB0
Gnd
RCOL1
Gnd
RCOL3
Gnd
RROW0
Gnd
RROW2
Gnd
NC
Gnd
RCFMN
Gnd
RCFM
Gnd
RDQA1
Gnd
RDQA3
Gnd
RDQA5
Gnd
RDQA7
Gnd
Page 2
Rev. 0.0/ Feb. 99
HYMR11696/11896 Series
Preliminary
Pin Definition
Signal
Gnd
Pins
A1, A3, A5, A7, A9, A11, A13, A15,
A17, A19, A21, A23, A25, A27, A29,
A31, A33, A39, A52, A60, A62, A64,
A66, A68, A70, A72, A74, A76, A78,
A80, A82, A84, A86, A88, A90, A92,
B1, B3, B5, B7, B9, B11, B13, B15,
B17, B19, B21, B23, B25, B27, B29,
B31, B33, B39, B52, B60, B62, B64,
B66, B68, B70, B72, B74, B76, B78,
B80, B82, B84, B86, B88, B90, B92
B10
I/O
Type
Description
Ground reference for RDRAM core and interface. 72
pins.
LCFM
I
RSL
Clock from master. Interface clock used for receiving
RSL signals from the Channel. Positive polarity.
Clock from master. Interface clock used for receiving
RSL signals from the Channel. Negative polarity.
Serial Command Pin. Pin used to read from and write to
the control registers. Also used for power management.
Column bus. 5-pin bus containing control and address
information for column accesses.
Clock to master. Interface clock used for transmitting
RSL signals to the Channel. Positive polarity.
Clock to master. Interface clock used for transmitting
RSL signals to the Channel. Negative polarity.
Data bus A. A 9-pin bus carrying a byte of read or write
data between the Channel and the RDRAM. LDQA8 is
non-functional on x16 devices
Data bus B. A 9-bit bus carrying a byte of read or write
data between the Channel and the RDRAM. LDQB8 is
non-functional on x16 devices.
Row bus. 3-pin bus containing control and address infor-
mation for row accesses.
Clock input. Pin used to read from and write to the con-
trol registers.
These pins are not connected. These 24 pins are all
reserved for future use.
LCFMN
B12
I
RSL
LCMD
B34
I
V
CMOS
RSL
LCOL4..
LCOL0
LCTM
A20, B20, A22, B22, A24
I
A14
I
RSL
LCTMN
A12
I
RSL
LDQA8..
LDQA0
A2, B2, A4, B4, A6, B6, A8, B8, A10
I/O
RSL
LDQB8..
LDQB0
B32, A32, B30, A30, B28, A28, B26,
A26, B24
I/O
RSL
LROW2..
LROW0
LSCK
B16, A18, B18
I
RSL
A34
I
V
CMOS
NC
A16, B14, A38, B38, A40, B40, A43,
B43, A44, B44, A45, B45, A46, B46,
A47, B47, A48, B48, A49, B49, A50,
B50, A77, B79
B83
I
RSL
RCFM
Clock from master. Interface clock used for receiving
RSL signals from the Channel. Positive polarity.
Clock from master. Interface clock used for receiving
RSL signals from the Channel. Negative polarity.
RCFMN
B81
I
RSL
Rev. 0.0/ Feb. 99
Page 3
Preliminary
HYMR11696/11896 Series
Signal
RCMD
Pins
B59
I/O
Type
Description
Serial Command Input. Pin used to read from and write
to the control registers. Also used for power manage-
ment.
Column bus. 5-pin bus containing control and address
information for column accesses.
Clock to master. Interface clock used for transmitting
RSL signals to the Channel. Positive polarity.
Clock to master. Interface clock used for transmitting
RSL signals to the Channel. Negative polarity.
Data bus A. A 9-pin bus carrying a byte of read or write
data between the Channel and the RDRAM. RDQA8 is
non-functional on x16 devices.
Data bus B. A 9-bit bus carrying a byte of read or write
data between the Channel and the RDRAM. RDQB8 is
non-functional on x16 devices.
Row bus. 3-pin bus containing control and address infor-
mation for row accesses.
Clock input. Pin used to read from and write to the con-
trol registers.
Serial Presence Detect Address 0.
Serial Presence Detect Address 1.
Serial Presence Detect Address 2.
Serial Presence Detect Clock.
Serial Presence Detect Data (Open Collector I/O).
Serial I/O. Pin for reading from and writing to the control
registers. Attaches to SIO0 of the first RDRAM on the
module.
Serial I/O. Pin for reading from and writing to the control
registers. Attaches to SIO1 of the last RDRAM on the
module.
SPD Voltage. Used for signals SCL, SDA, SWE, SA0,
SA1 and SA2.
I
V
CMOS
RCOL4..
RCOL0
RCTM
A73, B73, A71, B71, A69
I
RSL
A79
I
RSL
RCTMN
A81
I
RSL
RDQA8..
RDQA0
A91, B91, A89, B89, A87, B87, A85,
B85, A83
I/O
RSL
RDQB8..
RDQB0
B61, A61, B63, A63, B65, A65, B67,
A67, B69
I/O
RSL
RROW2..
RROW0
RSCK
B77, A75, B75
I
RSL
A59
I
I
I
I
I
I/O
V
CMOS
SV
DD
SV
DD
SV
DD
SV
DD
SV
DD
SA0
SA1
SA2
SCL
SDA
SIN
B53
B55
B57
A53
A55
B36
I/O
V
CMOS
SOUT
A36
I/O
V
CMOS
SV
DD
SWP
A56, B56
A57
I
SV
DD
Serial Presence Detect Write Protect (active high). When
low, the SPD can be written as well as read.
CMOS I/O Voltage. Used for signals CMD, SCK, SIN,
SOUT.
Supply voltage for the RDRAM core and interface logic.
V
CMOS
Vdd
A35, B35, A37, B37
A41, A42, A54, A58, B41, B42, B54,
B58
A51, B51
Vref
Logic threshold reference voltage for RSL signals.
Page 4
Rev. 0.0/ Feb. 99
1 per
2 RDRAMs
Plus one
Near Connector
0.1µF
2 per
RDRAM
0.1µF
V
CMOS
1 per
2 RDRAMs
0.1
µF
V
REF
Gnd
Gnd
Vdd
Gnd
U16
U1
U2
U3
SV
DD
.
.
.
0.1
µF
HYMR11696/11896 Series
Functional Diagram
.
.
.
SIN
LSCK
LCMD
V
REF
SOUT
Note 1: Rambus Channel signals form a loop through
the RIMM module, with the exception of the SIO chain.
LDQA8
LDQA7
LDQA6
LDQA5
LDQA4
LDQA3
LDQA2
LDQA1
LDQA0
LCFM
LCFMN
LCTM
LCTMN
LROW2
LROW1
LROW0
LCOL4
LCOL3
LCOL2
LCOL1
LCOL0
LDQB0
LDQB1
LDQB2
LDQB3
LDQB4
LDQB5
LDQB6
LDQB7
LDQB8
DQA8
DQA7
DQA6
DQA5
DQA4
DQA3
DQA2
DQA1
DQA0
CFM
CFMN
CTM
CTMN
ROW2
ROW1
ROW0
COL4
COL3
COL2
COL1
COL0
DQB0
DQB1
DQB2
DQB3
DQB4
DQB5
DQB6
DQB7
DQB8
DQA8
DQA7
DQA6
DQA5
DQA4
DQA3
DQA2
DQA1
DQA0
CFM
CFMN
CTM
CTMN
ROW2
ROW1
ROW0
COL4
COL3
COL2
COL1
COL0
DQB0
DQB1
DQB2
DQB3
DQB4
DQB5
DQB6
DQB7
DQB8
DQA8
DQA7
DQA6
DQA5
DQA4
DQA3
DQA2
DQA1
DQA0
CFM
CFMN
CTM
CTMN
ROW2
ROW1
ROW0
COL4
COL3
COL2
COL1
COL0
DQB0
DQB1
DQB2
DQB3
DQB4
DQB5
DQB6
DQB7
DQB8
DQA8
DQA7
DQA6
DQA5
DQA4
DQA3
DQA2
DQA1
DQA0
CFM
CFMN
CTM
CTMN
ROW2
ROW1
ROW0
COL4
COL3
COL2
COL1
COL0
DQB0
DQB1
DQB2
DQB3
DQB4
DQB5
DQB6
DQB7
DQB8
RDQA8
RDQA7
RDQA6
RDQA5
RDQA4
RDQA3
RDQA2
RDQA1
RDQA0
RCFM
RCFMN
RCTM
RCTMN
RROW2
RROW1
RROW0
RCOL4
RCOL3
RCOL2
RCOL1
RCOL0
RDQB0
RDQB1
RDQB2
RDQB3
RDQB4
RDQB5
RDQB6
RDQB7
RDQB8
Serial Presence Detect
SDA
Direct RDRAM (128/144Mb)
Direct RDRAM (128/144Mb)
Direct RDRAM (128/144Mb)
Direct RDRAM (128/144Mb)
Preliminary
SV
DD
SCL
SWP
SCL
SDA
WP
A0 A1 A2
Vcc
SIO0
SIO1
SCK
CMD
Vref
SIO0
SIO1
SCK
CMD
Vref
SIO0
SIO1
SCK
CMD
Vref
SIO0
SIO1
SCK
CMD
Vref
47K Ohm
SA0
SA1
SA2
U0
Gnd
RSCK
RCMD
Rev. 0.0/ Feb. 99
Page 5
stm32/stm8
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