Si32266/7/8/9
S
INGLE
- C
H IP
D
UAL
P
RO
S L I C
®
W I T H
I
NT EGR A TED
S
ERIAL
I
NTERFACE
(ISI)
Features
Two complete FXS channels in 6 x 8 mm
3-wire ISI combines PCM, SPI, and interrupt
Performs all BORSCHT functions
Ideal for short- or long-loop applications
Ultra low power consumption
Internal balanced or unbalanced ringing
Patented low power ringing
Adaptive ringing
Simplified configuration and diagnostics
Supported by ProSLIC API
GR-909 loop diagnostics
Audio diagnostics with loopback
Integrated test load
Wideband voice support
On-hook transmission
Loop or ground start operation
Smooth polarity reversal
Pulse metering
Software-programmable parameters:
Ringing frequency, amplitude,
cadence, and waveshape
Two-wire ac impedance
Transhybrid balance
DC current loop feed (10–45 mA)
Loop closure and ring trip thresholds
Ground key detect threshold
Integrated dc-dc controllers with direct
connection to MOSFET
Two high voltage supply options
Full tracking (Si32266/7)
Tracking shared supplies
(Si32268/9)
DTMF generator/decoder
A-Law/µ-Law companding, linear PCM
3.3 V operation
Pb-free/RoHS-compliant packaging
Ordering Information
See page 42.
Applications
VoIP gateways and routers
xDSL IADs
Optical Network Terminals/Units (ONT/U)
Analog Terminal Adapters (ATA)
Cable eMTA
Wireless Fixed Terminals (WFT)
Wireless Local Loop (WLL)
WiMAX CPE
TIPa
N/C
GPIO2A / SRINGCa
GPIO1a / STIPCa
SRINGDCa
SRINGACa
STIPACa
STIPDCa
CAPPa
CAPMa
SVBATa
SVDC
RSTB
PSCLK
Pin Assignments
Si32266/7
VREF_BT
VBATa
VBATb
RINGa
N/C
N/C
N/C
N/C
N/C
RINGb
41
50
48
58
47
57
49
46
45
44
43
42
40
N/C
39
38
37
Description
The Si32266/7/8/9 Dual ProSLIC® devices, in a single package, implement two complete
foreign exchange station (FXS) telephony interfaces. The Si32266/7/8/9 devices operate
from a 3.3 V supply and use Silicon Labs' proprietary three-wire digital Integrated Serial
Interface (ISI). Built-in dc-dc converter controllers can be used to automatically generate the
optimal battery voltage required for each line-state, optimizing efficiency and minimizing
heat generation. The Si32266/7 devices are designed to operate with a tracking battery
supply for each channel for lowest power consumption. The Si32268/9 devices use shared
battery supplies for lowest cost, with an internal dc-dc controller that operates in Tracking
Shared Supply (TSS) mode to deliver power consumption lower than typical fixed voltage
shared rail designs. Self-testing and metallic loop testing (MLT) (e.g., GR-909) is facilitated
by the built-in DSP, monitor ADC, and test load. The devices are available with linefeed
voltage ratings of –110 V (Si32266/8) or –140 V (Si32267/9) to support high voltage ringing,
and both devices support wideband audio for better-than-PSTN voice quality. All Si32266/7/
8/9 devices are available in a 6 x 8 mm 50-pin QFN package.
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
TIPb
N/C
VDDA
GPIO2b / SRINGCb
GPIO1b / STIPCb
SRINGDCb
SRINGACb
STIPACb
STIPDCb
IREF
CAPPb
CAPMb
SVBATb
VDDREG
EPAD 1
36
35
34
33
32
31
30
EPAD 2
29
28
27
26
DCDRVa
DCDRVb
SDCHa
SDCLa
DCFFa
Si32268/9
BASEa
VBATa
BAT_PO
BASEb
VBATb
N/C
RINGb
40
39
38
37
DCFFb
N/C
N/C
50
48
58
47
57
49
46
44
N/C
45
43
RINGa
N/C
TIPa
N/C
GPIO2a / SRINGCa
GPIO1a / STIPCa
SRINGDCa
42
41
N/C
SDCHb
SDCLb
VDDD
MISO
MOSI
25
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
N/C
TIPb
N/C
VDDA
GPIO2b / SRINGCb
GPIO1b / STIPCb
SRINGDCb
SRINGACb
STIPACb
STIPDCb
IREF
CAPPb
CAPMb
SVBATb
Functional Block Diagram
D TM F &
Tone G en
C a lle r ID
R in g in g
G e n e ra to r
Programmable
Programmable
AC Impedance
AC Impedance
and Hybrid
PCM/
Integrated Serial
Interface
M IS O
M OSI
EPAD 1
36
35
34
33
32
31
30
CODEC
ADC
ADC
DAC
DAC
CODEC
ADC
DAC
S L IC
Linefeed
L in e fe e d
C o n tro l
L in e fe e d
M o n ito r
SRINGACa
T IP
STIPACa
In te rfa c e
Channel A
R IN G
STIPDCa
CAPPa
CAPMa
SVBATa
SVDC
EPAD 2
29
28
27
26
Linefeed
VDDD
PS C LK
PLL
D C -D C C o n tro lle rs
D C -D C C o n tro lle r
L in e fe e d
M o n ito r
R IN G
S i3 2 2 6 6 /7 /8 /9
Patents pending
Rev. 1.2 2/13
Copyright © 2013 by Silicon Laboratories
DCDRVb
Si32266/7/8/9
VDDREG
PSCLK
SDCHb
DCFFa
DCFFb
SDCLb
RSTB
MISO
MOSI
L in e D ia g n o s tics
C hannel B
25
DSP
S L IC
L in e fe e d
C o n tro l
T IP
Si32266/7/8/9
T
ABLE
Section
OF
C
ONTENTS
Page
1. Electrical Specifications . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .5
2. Typical Application Circuits . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17
2.1. Si32266/7 Flyback Tracking DC-DC Converter . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17
2.2. Si32268 TSS DC-DC Converter . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20
3. Bill of Materials . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23
4. Functional Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28
5. FXS Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .29
5.1. DC Feed Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29
5.2. Linefeed Operating States . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29
5.3. Line Voltage and Current Monitoring . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29
5.4. Power Monitoring and Power Fault Detection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29
5.5. Thermal Overload Shutdown . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29
5.6. Loop Closure Detection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30
5.7. Ground Key Detection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30
5.8. Ringing Generation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31
5.9. Polarity Reversal . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 32
5.10. Two-Wire Impedance Synthesis . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 32
5.11. Transhybrid Balance Filter . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 32
5.12. Tone Generators . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 32
5.13. DTMF Detection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 32
5.14. Pulse Metering . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .32
5.15. DC-DC Controller . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 32
5.16. Wideband Audio . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 33
5.17. In-Circuit and Metallic Loop Testing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 33
6. Integrated Serial Interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .35
7. Pin Descriptions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 36
7.1. Si32266/7 Pin Assignments . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 36
7.2. Si32268/9 Pin Assignments . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 39
8. Ordering Guide . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 42
9. Product Identification . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .44
10. Package Outlines . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 45
10.1. 50-Pin QFN/LGA . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 45
10.2. 50-Pin QFN/NBA . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 46
11. PCB Land Pattern: LGA and NBA Packages . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 47
11.1. Land Pattern and Solder Mask Design . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 47
11.2. Thermal Via Layout . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .48
11.3. Stencil Aperture Design . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .49
12. Top Markings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 50
12.1. 50-Pin LGA Top Marking . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 50
12.2. 50-Pin LGA Top Marking Explanation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .50
12.3. 50-Pin NBA Top Marking . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 51
Rev. 1.2
3
Si32266/7/8/9
12.4. 50-Pin NBA Top Marking Explanation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .51
Document Change List: . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .53
Contact Information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .54
4
Rev. 1.2
Si32266/7/8/9
1. Electrical Specifications
Table 1. Recommended Operating Conditions
1
Parameter
Ambient Temperature
Silicon Junction Temperature,
QFN-50
Supply Voltage, Si3226x
Battery Voltage, Si32266/8
3
Battery Voltage, Si32267/9
3
Symbol
T
A
T
JHV
V
DDD
, V
DDA
V
BAT
V
BAT
Test Condition
F-grade
G-grade
Linefeed Die
Min
0
–40
—
3.13
–110
–140
Typ
25
25
—
3.3
—
—
Max
70
85
145
2
3.47
–15
–15
Unit
°C
°C
°C
V
V
V
Notes:
1.
All minimum and maximum specifications apply across the recommended operating conditions. Typical values apply at
nominal supply voltages and an operating temperature of 25
°
C unless otherwise stated.
2.
Except during ringing.
3.
Operation at minimum voltage dependent upon loop conditions and dc-dc converter configuration.
Table 2. AC Characteristics
(V
DD
= 3.13 to 3.47 V, T
A
= 0 to 70 °C)
Parameter
Overload Compression
Single Frequency Distortion
(0 dBm0 input)
Signal-to-(Noise + Distortion) Ratio
1
Test Condition
TX/RX Performance
2-Wire – PCM
0 Hz to 4 kHz
0 Hz to 12 kHz
200 Hz to 3.4 kHz
D/A or A/D 8-bit
Active off-hook, and OHT, any Z
T
0 dBm0, Active off-hook, and
OHT, any Z
T
2-Wire to PCM or PCM to 2-Wire
1014 Hz, any gain setting
0 dBm0
5
Min
Figure 4
—
—
Figure 3
Typ
—
—
—
—
Max
—
–40
–28
—
Unit
dBm0
5
dBm0
5
Audio Tone Generator Signal-to-
Distortion Ratio
1
Intermodulation Distortion
Gain Accuracy
1
Attenuation Distortion vs. Frequency
Group Delay vs. Frequency
46
—
–0.2
—
—
—
—
–41
0.2
dB
dB
dB
See Figure 5 and 6
See Figure 7 and 8
Notes:
1.
Analog signal measured as V
TIP
– V
RING
. Assumes ideal line impedance matching.
2.
The quantization errors inherent in the µ/A-law companding process can generate slightly worse gain tracking
performance in the signal range of 3 to –37 dB for signal frequencies that are integer divisors of the 8 kHz PCM
sampling rate.
3.
V
DDD
, V
DDA
= 3.3 V, V
BAT
= –52 V, no fuse resistors; R
L
= 600
,
Z
S
= 600
synthesized using RS register
coefficients.
4.
The level of any unwanted tones within the bandwidth of 0 to 4 kHz does not exceed –55 dBm.
5.
0 dBm0 is equal to 0 dBm into 600
.
Rev. 1.2
5
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