CML Semiconductor Products
PRODUCT INFORMATION
FX029
Dual Digitally Controlled
Amplifier Array
Applications
Cellular and PMR
Communications Systems
Automatic and Manual Test
Equipment
Remote Gain Adjustments
Telephone Audio Settings
Medical Equipment
Audio and Data Gain Setting
Applications
Publication D/029/3 April 1997
Provisional Issue
Features
2 Digitally Controlled Amplifiers
Gain/Attenuation Range of ±48dB
+ Output Mute, in 2dB Steps
Gain/Attenuation Levels Set by
Serial Interface
Separate Fixed-Gain Uncommitted
Amplifier
5 Volt Low-Power Operation
SERIAL CLOCK
SERIAL DATA
LOAD/LATCH
STAGE 1
CONTROL
REGISTER
Gain
Control 1
SERIAL
INTERFACE
STAGE 2
CONTROL
REGISTER
Control 2
Gain
IN 1A
IN 1B
IN 1C
6
6
IN 2A
IN 2B
Stage 1
V
BIAS
V
BIAS
Stage 2
Stage 2 Inputs
FX029
Stage 1 Inputs
V
DD
V
BIAS
V
SS
Control 1
Control 2
-
+
V
SS
V
SS
Stage 3
(UNCOMMITTED)
IN 3
Stage 3 Input
V
BIAS
OUTPUTS
1A
1B
2
3
Fig.1 Functional Block Diagram
Brief Description
The FX029 single-chip Dual Digitally Controlled
Amplifier Array can replace manual audio-level
controls in most electronic applications including radio
and line communications systems.
The FX029 comprises two digitally controlled gain
and attenuation stages, with each stage having 48
distinct gain steps (range; between -48dB and +48dB
in 2dB steps) plus a MUTE state to powersave the
addressed section. Minimum current drain results from
muting both sections.
Both gain stages have selectable inputs. This
switching allows for selection of three different input
signals to stage 1 and two to stage 2.
1
Stage 1 also provides output switching.
In addition to the two digitally controlled gain stages,
there is a general purpose, uncommitted inverting
amplifier; the gain of this particular amplifier is
component controlled externally using negative
feedback.
Control of each gain stage section is accomplished
through the serial interface. All switching is
accomplished using controlled rise and fall times,
thereby ensuring no annoying transients (clicks or
pops).
The FX029 requires a single 5 volt supply and is
available in compact cerdip and small outline packages.
Pin Number
FX029
DW/J
D5
1
1
Function
Serial Clock:
This external clock input is used to “clock in” the control data. See Figure 4 for
timing information. This input has an internal 1MΩ pullup resistor.
2
4
Serial Data:
Operation of the two amplifier stages (1 and 2) is controlled by the data entered
serially at this pin. The data is entered (bit 13 to bit 0) on the rising edge of the external Serial
Clock. The data format is described in Tables 1-3 and Figure 4.
This input has an internal 1MΩ pullup resistor.
3
5
Load/Latch:
Governs the loading and execution of the serial control data. During serial data
loading this input should be kept at a logical “1” to ensure that data rippling past the latches
has no effect. When all 14 bits have been loaded this input should be strobed “1” to “0” to “1” to
latch the new data in. Data is executed on the rising edge of this strobe.
4
6
IN 1A
(Stage 1 Input 1): Analogue Input.
5
7
IN 1B
(Stage 1 Input 2): Analogue Input.
6
8
IN 2A
(Stage 2 Input 1): Analogue Input.
7
9
IN 2B
(Stage 2 Input 2): Analogue Input.
8
12
V
SS
:
Negative supply rail (GND).
9
13
V
BIAS
:
The output of the on-chip bias circuitry, held at V
DD
/2.
10
16
IN 1C
(Stage 1 Input 3): Analogue Input. Normally used for FSK data.
11
17
OUT 2
(Stage 2 Output): Analogue Output.
12
18
OUT 1B
(Stage 1 Output 2): Analogue Output.
13
20
OUT 1A
(Stage 1 Output 1): Analogue Output.
14
21
OUT 3
(Uncommitted Amplifier Output): Output from the general purpose uncommitted
amplifier.
15
23
IN 3
(Uncommitted Amplifier Input): Inverting input to general purpose uncommitted amplifier.
16
24
V
DD
:
Positive supply rail. A single +5-volt power supply is required.
2
Application Information
External Components
V
DD
SERIAL CLOCK
SERIAL DATA
LOAD/LATCH
IN 1A
IN 1B
IN 2A
IN 2B
C
1
C
2
C
3
C
4
V
SS
8
1
2
3
4
16
15
14
13
V
DD
IN 3
OUT 3
C
7
V
SS
OUT 1A
OUT 1B
OUT 2
C
5
V
BIAS
IN 1C
FX029
5
6
7
DW/J
12
11
10
9
V
SS
Fig.2 Recommended External Components
Component Recommendations
Component
Value
C
1
0.1µF
C
2
0.1µF
C
3
0.1µF
C
4
0.1µF
C
5
0.1µF
C
6
Not Used
C
7
1.0µF
Tolerances 20%
Input capacitors C
1
to C
5
are only required for ac
input signals; dc input signals do not require these
components.
The gain of the uncommitted stage (3) is set by
external components employed around the input and
output pins (see Specification page).
Application Recommendations
To avoid noise and instability the following practices
are recommended:
(a) Use a clean, well-regulated power supply.
(b) Keep tracks short.
(c) Inputs and outputs should be shielded wherever
possible.
(d) Analogue tracks should not run parallel to digital
tracks.
(e) A “Ground Plane” connected to V
SS
will assist in
eliminating external pick-up on the channel input
and output pins.
(f) Avoid running high level outputs adjacent to low
level inputs.
(g) The serial clock should not be running
consecutively when not in the process of actually
loading data.
Serial Interface Timing
SERIAL
CLOCK
t
PWH
t
PWL
1ST
CLOCK
PULSE
14TH
CLOCK
PULSE
SERIAL
DATA
t
DS
D13
t
DH
D12
D1
D0
LOAD/LATCH
t
LLD
t
LLO
Fig.3 Serial Timing Diagram - see Specification page for timing specifications
3
t
LLW
Control Data and Timing
The gain and I/O signal path for each section (Channels 1 and 2) is set individually by a 14-bit data word (D0 to
D13). Data is loaded on the rising edge of the Serial Clock. Loaded data is executed on the rising edge of the Load/
Latch pulse.The 14-bit word consists of 1 channel address bit (D7) for selection of the channel to be programmed,
6 bits for setting the amplification/attenuation level (D8-D13), 3 bits for input selection (D4 and D6), and 4 bits for
output settings (D0-D3). This format is illustrated below in Figure 4.
Tables 1-3 show how the data word is used to control channel selection, amplification/attenuation, input selection
and output settings, respectively.
D13
D12
D12
D10
D9
D8
D7
D6
D5
INPUT
SELECT
D4
D3
D2
D1
D0
GAIN/ATTENUATION
LEVEL
CHANNEL
ADDRESS
OUTPUT
SETTINGS
Fig.4 Level-Controlling Data Word Format
D13 D12 D11 D10
Gain
Set (dB)
0
0
0
0
0
0
MUTE
0
0
0
0
0
1
-48
0
0
0
0
1
0
-46
0
0
0
0
1
1
-44
0
0
0
1
0
0
-42
0
0
0
1
0
1
-40
0
0
0
1
1
0
-38
0
0
0
1
1
1
-36
0
0
1
0
0
0
-34
0
0
1
0
0
1
-32
0
0
1
0
1
0
-30
0
0
1
0
1
1
-28
0
0
1
1
0
0
-26
0
0
1
1
0
1
-24
0
0
1
1
1
0
-22
0
0
1
1
1
1
-20
0
1
0
0
0
0
-18
0
1
0
0
0
1
-16
0
1
0
0
1
0
-14
0
1
0
0
1
1
-12
0
1
0
1
0
0
-10
0
1
0
1
0
1
-8
0
1
0
1
1
0
-6
0
1
0
1
1
1
-4
0
1
1
0
0
0
-2
0
1
1
0
0
1
0
Table 1 - Amplification/Attenuation Level
D9
D8
D13 D12 D11 D10
D9
D8
0
0
0
0
0
0
0
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
1
1
1
1
1
1
1
1
1
1
1
0
0
0
0
0
0
0
0
1
1
1
1
1
1
1
1
0
0
0
0
0
0
0
1
1
1
1
0
0
0
0
1
1
1
1
0
0
0
0
1
1
1
1
0
0
0
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
Gain
Set (dB)
0
2
4
6
8
10
12
14
16
18
20
22
24
26
28
30
32
34
36
38
40
42
44
46
48
48
48
D7
0
1
0
0
0
0
0
1
0
1
1
0
1
0
1
1
1
1
Table 2 Stage and Input Selection
Stage
Selected
1
2
D6
D5
D4
0
1
0
1
0
1
0
1
Inputs
Selected
none
1
2
1 and 2
3
1 and 3
2 and 3
1, 2 and 3
Output
D1
1B
0
0
high Z
0
0
1
enabled
0
1
0
V
SS
1
1
1
V
BIAS
1
Table 3 Stage Output Selection
D3 D2
D0
0
1
0
1
Outputs
1A & 2
high Z
enabled
V
SS
V
BIAS
4
Specification
Absolute Maximum Ratings
Exceeding the maximum rating can result in device damage. Operation of the device outside the operating limits
is not implied.
Supply voltage
-0.3 to 7.0V
Input voltage at any pin (ref. V
SS
= 0V)
-0.3 to (V
DD
+ 0.3V)
Sink/source current (supply pins)
+/- 30mA
(other pins)
+/- 20mA
Total device dissipation (DW/J) @ T
AMB
25°C
(D5) @ T
AMB
25°C
Derating
(DW/J)
(D5)
Operating temperature range:
FX029DW/D5/J
Storage temperature range:
FX029D5
FX029DW/J
800mW Max.
550mW Max.
10mW/°C
9mW/°C
-40°C to +85°C
-40°C to +85°C
-55°C to +125°C
Operating Characteristics
All device characteristics are measured under the following conditions unless otherwise specified:
V
DD
= 5.0V, T
AMB
= 25°C. External components as Figure 2. Audio 0dB ref. = 775mVrms
Characteristics
See Note
Min.
4.5
-
-
3.5
-
0.5
3.3
-
-
-
46.0
46.0
-
-
50.0
-
10.0
-
-
-
250
250
150
50.0
200
-
150
-
Typ.
5.0
0.10
3.0
-
-
1.0
-
1.0
0.35
60.0
48.0
48.0
2.0
-
-
10.0
-
1.0
0.35
60
-
-
-
-
-
-
-
-
Max.
5.5
-
-
-
1.5
-
-
2.0
0.5
-
-
-
-
0.4
-
-
-
2.0
0.5
-
-
-
-
-
-
0
-
2.0
Unit
V
mA
mA
V
V
MΩ
kHz
kΩ
%
dB
dB
dB
dB/step
dB
kΩ
mV
kHz
kΩ
%
dB
ns
ns
ns
ns
ns
ns
ns
MHz
Supply Voltage
Current
(All Stages Mute)
(All Stages Operating)
Digital Inputs
4
Input Logic “1”
Input Logic “0”
Digital Input Impedances
Gain Control Amplifier Stages
(Stages 1 and 2)
Bandwidth (-3dB)
1
Output Impedance
Total Harmonic Distortion
2, 5
Interstage Isolation
Gain
Attenuation
Gain/Attenuation Step Size
Step Error
Input Impedance
Input Referred Offset Voltage (V
IOS
)
Uncommitted Amplifier
(Stage 3)
Bandwidth (-3dB)
3
Output Impedance
Total Harmonic Distortion
3
Open Loop DC Gain
Timing
(See Figure 3)
Serial Clock “High” Pulse Width (t
PWH
)
Serial Clock “Low” Pulse Width (t
PWL
)
Data Set-up Time (t
DS
)
Data Hold Time (t
DH
)
Load/Latch Delay (t
LLD
)
Load/Latch Over-Time (t
LLO
)
Load/Latch Pulse Width (t
LLW
)
Serial Data Clock Frequency
Notes
1.
2.
3.
4.
5.
Gain set to maximum (+48.0dB).
Gain Set 0dB. Input Level 1.0kHz, -3.0dB (549mVrms).
Gain externally set to 10.0dB.
Serial Clock, Serial Data and Load/Latch inputs.
With a 100kΩ load on the relevant output.
5
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