LD3985
SERIES
ULTRA LOW DROP-LOW NOISE BICMOS VOLTAGE
REGULATORS LOW ESR CAPACITORS COMPATIBLE
s
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INPUT VOLTAGE FROM 2.5V TO 6V
STABLE WITH LOW ESR CERAMIC
CAPACITORS
ULTRA LOW DROPOUT VOLTAGE (100mV
TYP. AT 150mA LOAD, 0.4mV TYP. AT 1mA
LOAD)
VERY LOW QUIESCENT CURRENT (85µA
TYP. AT NO LOAD, 170µA TYP. AT 150mA
LOAD; MAX 1.5µA IN OFF MODE)
GUARANTEED OUTPUT CURRENT UP TO
150mA
WIDE RANGE OF OUTPUT VOLTAGE:
1.25V; 1.35; 1.5; 1.8V; 2V; 2.1V; 2.2V; 2.4V;
2.5V; 2.6V; 2.7V; 2.8V; 2.85V; 2.9V; 3V; 3.1V;
3.2V; 3.3V; 4.7V; 5V
FAST TURN-ON TIME: TYP. 200µs [C
O
=1µF,
C
BYP
= 10nF AND I
O
=1mA]
LOGIC-CONTROLLED ELECTRONIC
SHUTDOWN
INTERNAL CURRENT AND THERMAL LIMIT
OUTPUT LOW NOISE VOLTAGE 30µVRMS
OVER 10Hz to 100KHz
S.V.R. OF 60dB AT 1KHz, 50dB AT 10KHz
TEMPERATURE RANGE: -40°C TO 125°C
Flip-Chip
(1.57x1.22)
SOT23-5L
TSOT23-5L
DESCRIPTION
The LD3985 provides up to 150mA, from 2.5V to
6V input voltage.
SCHEMATIC DIAGRAM
The ultra low drop-voltage, low quiescent current
and low noise make it suitable for low power
applications and in battery powered systems.
Regulator ground current increases only slightly in
dropout, further prolonging the battery life. Power
supply rejection is better than 60 dB at low
frequencies and starts to roll off at 10KHz. High
power supply rejection is maintained down to low
input voltage levels common to battery operated
circuits. Shutdown Logic Control function is
available, this means that when the device is used
as local regulator, it is possible to put a part of the
board in standby, decreasing the total power
consumption. The LD3985 is designed to work
with low ESR ceramic capacitors. Typical
applications are in mobile phone and similar
battery powered wireless systems.
December 2003
1/13
LD3985 SERIES
ABSOLUTE MAXIMUM RATINGS
Symbol
V
I
V
O
V
INH
I
O
P
D
T
STG
T
OP
DC Input Voltage
DC Output Voltage
INHIBIT Input Voltage
Output Current
Power Dissipation
Storage Temperature Range
Operating Junction Temperature Range
Parameter
Value
-0.3 to 6 (*)
-0.3 to V
I
+0.3
-0.3 to V
I
+0.3
Internally limited
Internally limited
-65 to 150
-40 to 125
°C
°C
Unit
V
V
V
Absolute Maximum Ratings are those values beyond which damage to the device may occur. Functional operation under these condition is
not implied.
(*) The input pin is able to withstand non repetitive spike of 6.5V for 200ms.
THERMAL DATA
Symbol
Parameter
SOT23-5L/
TSOT23-5L
81
255
170
Flip-Chip
Unit
°C/W
°C/W
R
thj-case
Thermal Resistance Junction-case
R
thj-amb
Thermal Resistance Junction-ambient
CONNECTION DIAGRAM
(top view for SOT and TSOT, top through view for Flip-Chip)
TSOT23-5L/SOT23-5L
Flip-Chip
PIN DESCRIPTION
Pin N°
SOT23-5L/
TSOT235L
1
2
3
4
5
Pin N°
Flip-Chip
4
2
1
5
3
Symbol
V
I
GND
V
INH
BYPASS
V
O
Input Voltage of the LDO
Common Ground
Inhibit Input Voltage: ON MODE when V
INH
≥
1.2V, OFF MODE when V
INH
≤
0.4V (Do not leave floating, not internally pulled down/up)
Bypass Pin: Connect an external capacitor (usually 10nF) to minimize noise
voltage
Output Voltage of the LDO
Name and Function
2/13
LD3985 SERIES
ELECTRICAL CHARACTERISTICS FOR LD3985
(T
j
= 25°C, V
I
= V
O(NOM)
+0.5V, C
I
= 1µF,
C
BYP
= 10nF, I
O
= 1mA, V
INH
= 1.4V, unless otherwise specified)
Symbol
V
I
V
O
∆V
O
∆V
O
Parameter
Operating Input Voltage
Output Voltage
Line Regulation (Note 1)
Load Regulation
I
O
= 1 mA
T
J
= -40 to 125
°C
V
I
= V
O(NOM)
+ 0.5 to 6 VT
J
= -40 to 125
°C
V
O
= 4.7 to 5V
I
O
= 1 mA to 150mA (for Flip Chip)
T
J
= -40 to 125
°C
Test Conditions
Min.
2.5
-2
-3
-0.1
-0.19
0.0004
0.0025
1.5
85
T
J
= -40 to 125
°C
170
T
J
= -40 to 125
°C
0.003
T
J
= -40 to 125
°C
V
DROP
Dropout Voltage (NOTE 1) I
O
= 1mA
I
O
= 1mA
I
O
= 50mA
I
O
= 50mA
I
O
= 100mA
I
O
= 100mA
I
O
= 150mA
I
O
= 150mA
I
SC
SVR
Short Circuit Current
Supply Voltage Rejection
R
L
= 0
V
I
= V
O(NOM)
+0.25V ±
f = 1KHz
V
RIPPLE
= 0.1V, I
O
= 50mA f = 10KHz
V
O(NOM)
< 2.5V,
V
I
= 2.55V
V
O
≥
V
O(NOM)
- 5%
V
I
= 2.5V to 6V
V
INH
= 0.4V
C
BYP
= 10 nF
Note 5
Capacitance (Note 6)
ESR
1
5
T
J
= -40 to 125
°C
1.2
V
I
= 6V
C
O
= 1
µF
±1
30
200
160
22
5000
nA
µV
RMS
µs
°C
µF
mΩ
B
W
= 10 Hz to 100 KHz
300
T
J
= -40 to 125
°C
600
60
50
550
0.4
T
J
= -40 to 125
°C
60
100
mA
dB
T
J
= -40 to 125
°C
45
70
T
J
= -40 to 125
°C
20
35
0.4
2
1.5
mV
250
150
Typ.
Max.
6
2
3
0.1
0.19
0.002
0.005
mV
PP
µA
%/mA
Unit
V
% of
V
O(NOM)
%/V
∆V
O
I
Q
I
O
= 1 mA to 150mA, T
J
= -40 to 125
°C
(for SOT23-5L/TSOT23-5L)
Output AC Line Regulation V
I
= V
O(NOM)
+ 1 V, I
O
= 150mA,
t
R
= t
F
= 30µs
Quiescent Current
ON MODE: V
INH
= 1.2V
I
O
= 0
I
O
= 0
I
O
= 0 to 150mA
I
O
= 0 to 150mA
OFF MODE: V
INH
= 0.4V
I
O(PK)
V
INH
I
INH
eN
t
ON
T
SHDN
C
O
Peak Output Current
Inhibit Input Logic Low
Inhibit Input Logic High
Inhibit Input Current
Output Noise Voltage
Turn On Time (Note 4)
Thermal Shutdown
Output Capacitor
mA
V
Note 1 – For V
O(NOM)
< 2V, V
I
= 2.5V
Note 2 – For V
O(NOM)
= 1.25V, V
I
= 2.5V
Note 3 – Dropout voltage is the input-to-output voltage difference at which the output voltage is 100mV below its nominal value. This speci-
fication does not apply for input voltages below 2.5V.
Note 4 – Turn-on time is time measured between the enable input just exceeding V
INH
High Value and the output voltage just reaching 95%
of its nominal value
Note 5 – Typical thermal protection hysteresis is 20°C
Note 6 - The minimum capacitor value is 1µF, anyway the LD3985 is still stable if the compensation capacitor has a 30% tolerance in all
temperature range.
4/13
LD3985 SERIES
TYPICAL PERFORMANCE CHARACTERISTICS
(T
j
= 25°C, V
I
= V
O(NOM)
+0.5V, C
I
= C
O
= 1µF,
C
BYP
= 10nF, I
O
= 1mA, V
INH
= 1.4V, unless otherwise specified)
Figure 1 :
Output Voltage vs Temperature
Figure 4 :
Shutdown Voltage vs Temperature
Figure 2 :
Output Voltage vs Temperature
Figure 5 :
Shutdown Voltage vs Temperature
Figure 3 :
Output Voltage vs Temperature
Figure 6 :
Line Regulation vs Temperature
5/13
FPGA/CPLD
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