SU564288FD8NZCU
May 30, 2007
Ordering Information
Part Numbers
SM564288FD8NZCL
Description
128Mx64 (1GB), DDR, 200-pin SO-DIMM, Unbuffered,
Non-ECC, 64Mx8 Based, DDR333B, 31.75mm, 22Ω DQ
termination.
128Mx64 (1GB), DDR, 200-pin SO-DIMM, Unbuffered,
Non-ECC, 64Mx8 Based, DDR333B, 31.75mm, 22Ω DQ
termination, Green Module (RoHS Compliant).
128Mx64 (1GB), DDR, 200-pin SO-DIMM, Unbuffered,
Non-ECC, 64Mx8 Based, DDR266A, 31.75mm, 22Ω DQ
termination.
128Mx64 (1GB), DDR, 200-pin SO-DIMM, Unbuffered,
Non-ECC, 64Mx8 Based, DDR266A, 31.75mm, 22Ω DQ
termination, Green Module (RoHS Compliant).
128Mx64 (1GB), DDR, 200-pin SO-DIMM, Unbuffered,
Non-ECC, 64Mx8 Based, DDR266B, 31.75mm, 22Ω DQ
termination, Green Module (RoHS Compliant).
Module Speed
PC2700 @ CL 2.5
SG564288FD8NZCL
PC2700 @ CL 2.5
SM564288FD8NZCG
PC2100 @ CL 2.0, 2.5
SG564288FD8NZCG
PC2100 @ CL 2.0, 2.5
SG564288FD8NZCH
PC2100 @ CL 2.5
(All specifications of this device are subject to change without notice.)
Corporate Headquarters:
P. O. Box 1757, Fremont, CA 94538, USA • Tel:(510) 623-1231 • Fax:(510) 623-1434 • E-mail: info@smartm.com
Europe:
5 Kelvin Park South, Kelvin South, East Kilbride, G75 ORH, United Kingdom • Tel: +44-870-870-8747 • Fax: +44-870-870-8757
Asia/Pacific:
Plot 18, Lrg Jelawat 4, Kawasan Perindustrian Seberang Jaya 13700, Prai, Penang, Malaysia • Tel: +604-3992909 • Fax: +604-3992903
1
SU564288FD8NZCU
May 30, 2007
Revision History
• May 30, 2007
Changed the datasheet part number from SU564288FD8NZCL to SU564288FD8NZCU because of the addition
of new Module Speeds.
Added SM564288FD8NZCG, SG564288FD8NZCG & SG564288FD8NZCH to the datasheet to represent the
new Module Speeds.
Obsoleted SB564288FD8NZCL from the Ordering Information on page 1 because the Module Process Technol-
ogy is no longer supported.
• January 12, 2005
Obsoleted SX564288FD8NZCL from the Ordering Information on page 1 because the Mixed Process technology
is not supported for FBGA devices.
• September 27, 2004
Changed the datasheet part number from SM564288FD8NZCL to SU564288FD8NZCL because of the addition
of new Module Process Technologies.
Added SB564288FD8NZCL, SX564288FD8NZCL & SG564288FD8NZCL to the datasheet to represent the new
Module Process Technologies.
Updated the datasheet with the new Smart Modular logo.
• October 3, 2003
Updated byte 22 device attribute from 80h to C0h on page 9.
Changed V
DDSPD
max from 2.7 to 5.5 on page 15.
Updated DC Characteristic Currents on page 17.
• January 14, 2003
Datasheet released.
Corporate Headquarters:
P. O. Box 1757, Fremont, CA 94538, USA • Tel:(510) 623-1231 • Fax:(510) 623-1434 • E-mail: info@smartm.com
Europe:
5 Kelvin Park South, Kelvin South, East Kilbride, G75 ORH, United Kingdom • Tel: +44-870-870-8747 • Fax: +44-870-870-8757
Asia/Pacific:
Plot 18, Lrg Jelawat 4, Kawasan Perindustrian Seberang Jaya 13700, Prai, Penang, Malaysia • Tel: +604-3992909 • Fax: +604-3992903
2
SU564288FD8NZCU
May 30, 2007
1GByte (128Mx64) DDR SDRAM Module - 64Mx8 Based
200-pin SO-DIMM, Unbuffered, Non-ECC
Features
• Standard
• Configuration
• Cycle Time
•
•
•
•
:
:
:
JEDEC
Non-ECC
6.0ns (PC2700)
7.5ns (PC2100)
2.0, 2.5
2, 4, 8
Sequential/Interleave
4
•
•
•
•
•
•
•
Operating Voltage :
2.5V
Refresh
:
8K/64ms
Device Physicals :
FBGA
Lead Finish
:
Gold
Length x Height
:
67.60mm x 31.75mm
No. of sides
:
Double-sided
Mating Connector (Examples)
Horizontal
:
AMP - 1612618-1
CAS# Latency
:
Burst Length
:
Burst Type
:
No. of Internal
Banks per SDRAM :
DDR 200-pin SO-DIMM Pin List
Pin Pin
No. Name
1
3
5
7
9
11
13
15
17
19
21
23
25
27
29
31
33
35
37
39
41
V
REF
V
SS
DQ0
DQ1
V
DD
DQS0
DQ2
V
SS
DQ3
DQ8
V
DD
DQ9
DQS1
V
SS
DQ10
DQ11
V
DD
CLK0
CLK0#
V
SS
DQ16
Pin Pin
No. Name
2
4
6
8
10
12
14
16
18
20
22
24
26
28
30
32
34
36
38
40
42
V
REF
V
SS
DQ4
DQ5
V
DD
DM0
DQ6
V
SS
DQ7
DQ12
V
DD
DQ13
DM1
V
SS
DQ14
DQ15
V
DD
V
DD
V
SS
V
SS
DQ20
Pin Pin
No. Name
51
53
55
57
59
61
63
65
67
69
71
73
75
77
79
81
83
85
87
89
91
V
SS
DQ19
DQ24
V
DD
DQ25
DQS3
V
SS
DQ26
DQ27
V
DD
NC
NC
V
SS
NC
NC
V
DD
NC
DU
V
SS
CLK2
CLK2#
Pin Pin
No. Name
52
54
56
58
60
62
64
66
68
70
72
74
76
78
80
82
84
86
88
90
92
V
SS
DQ23
DQ28
V
DD
DQ29
DM3
V
SS
DQ30
DQ31
V
DD
NC
NC
V
SS
NC
NC
V
DD
NC
DU
V
SS
V
SS
V
DD
Pin Pin
No. Name
101 A9
103 V
SS
105 A7
107 A5
109 A3
111 A1
113 V
DD
115 A10/AP
117 BA0
119 WE#
121 CS0#
123 DU
125 V
SS
127 DQ32
129 DQ33
131 V
DD
133 DQS4
135 DQ34
137 V
SS
139 DQ35
141 DQ40
Pin Pin
No. Name
102 A8
104 V
SS
106 A6
108 A4
110 A2
112 A0
114 V
DD
116 BA1
118 RAS#
120 CAS#
122 CS1#
124 DU
126 V
SS
128 DQ36
130 DQ37
132 V
DD
134 DM4
136 DQ38
138 V
SS
140 DQ39
142 DQ44
Pin Pin
No. Name
151 DQ42
153 DQ43
155 V
DD
157 V
DD
159 V
SS
161 V
SS
163 DQ48
165 DQ49
167 V
DD
169 DQS6
171 DQ50
173 V
SS
175 DQ51
177 DQ56
179 V
DD
181 DQ57
183 DQS7
185 V
SS
187 DQ58
189 DQ59
191 V
DD
Pin Pin
No. Name
152 DQ46
154 DQ47
156 V
DD
158 CLK1#
160 CLK1
162 V
SS
164 DQ52
166 DQ53
168 V
DD
170 DM6
172 DQ54
174 V
SS
176 DQ55
178 DQ60
180 V
DD
182 DQ61
184 DM7
186 V
SS
188 DQ62
190 DQ63
192 V
DD
Corporate Headquarters:
P. O. Box 1757, Fremont, CA 94538, USA • Tel:(510) 623-1231 • Fax:(510) 623-1434 • E-mail: info@smartm.com
Europe:
5 Kelvin Park South, Kelvin South, East Kilbride, G75 ORH, United Kingdom • Tel: +44-870-870-8747 • Fax: +44-870-870-8757
Asia/Pacific:
Plot 18, Lrg Jelawat 4, Kawasan Perindustrian Seberang Jaya 13700, Prai, Penang, Malaysia • Tel: +604-3992909 • Fax: +604-3992903
3
SU564288FD8NZCU
May 30, 2007
DDR 200-pin SO-DIMM Pin List (Contd.)
Pin Pin
No. Name
43
45
47
49
DQ17
V
DD
DQS2
DQ18
Pin Pin
No. Name
44
46
48
50
DQ21
V
DD
DM2
DQ22
Pin Pin
No. Name
93
95
97
99
V
DD
CKE1
NC
A12
Pin Pin
No. Name
94
96
98
V
DD
CKE0
NC
Pin Pin
No. Name
143 V
DD
145 DQ41
147 DQS5
149 V
SS
Pin Pin
No. Name
144 V
DD
146 DQ45
148 DM5
150 V
SS
Pin Pin
No. Name
193 SDA
195 SCL
197 V
DDSPD
1
199 V
DDID
Pin Pin
No. Name
194 SA0
196 SA1
198 SA2
200 DU
100 A11
Note:
1. Pin 199 (V
DDID
) is not connected on this module. Therefore V
DDQ
of all the DDR devices is same as V
DD
.
Pin Description Table
Symbol
CLK0, CLK0#
CLK1, CLK1#
CLK2, CLK2#
CKE0, CKE1
CS0#, CS1#
Type
SSTL
(Inputs)
Polarity
Crossing Point
Function
The system clock inputs. All address and command lines are sampled on the cross point of
the rising edge of CLK and falling edge of CLK#. A Delay Locked Loop (DLL) circuit is
driven from the clock inputs and output timing for read operations is synchronized to the
input clock.
Activates the SDRAM CLK signal when high and deactivates the CLK signal when low. By
deactivating the clocks, CKE low initiates the Power Down mode, or the Self Refresh mode.
Enables the associated DDR SDRAM command decoder when low and disables decoder
when high. When decoder is disabled, new commands are ignored but previous operations
continue.
When sampled at the positive rising edge of the clock, CAS#, RAS#, and WE# define the
operations to be executed by the SDRAM.
Selects which of the four internal SDRAM banks is activated.
During a Bank Activate command cycle, A0-A12 defines the row address (RA0-RA12)
when sampled at the rising clock edge.
During a Read or Write command cycle, A0-A9, A11 defines the column address (CA0-
CA9, CA11) when sampled at the rising clock edge. In addition to the column address, A10/
AP is used to invoke autoprecharge operation at the end of the burst read or write cycle. If
AP is high, autoprecharge is selected and BA0, BA1 defines the bank to be precharged. If
AP is low, autoprecharge is disabled.
During a Precharge command cycle, A10/AP is used in conjunction with BA0, BA1 to con-
trol which bank(s) to precharge. If AP is high, all banks will be precharged regardless of the
state of BA0 or BA1. If AP is low, BA0 and BA1 are used to define which bank to precharge.
Data Input/Output pins.
The data write masks, associated with one data byte. In Write mode, DM operates as a byte
mask by allowing input data to be written if it is low but blocks the write operation if it is high.
In Read mode, DM lines have no effect.
The data strobes, associated with one data byte, sourced with data transfers. In Write
mode, the data strobe is sourced by the controller and is centered in the data window. In
Read mode, the data strobe is sourced by the DDR SDRAMs and is sent at the leading
edge of the data window.
SSTL
SSTL
Active High
Active Low
RAS#, CAS#,
WE#
BA0, BA1
A0~A9,
A10/AP,
A11~A12
SSTL
SSTL
SSTL
Active Low
-
-
DQ0~DQ63
DM0~DM7
SSTL
SSTL
-
Active High
DQS0~DQS7
SSTL
Negative &
Positive Edge
Corporate Headquarters:
P. O. Box 1757, Fremont, CA 94538, USA • Tel:(510) 623-1231 • Fax:(510) 623-1434 • E-mail: info@smartm.com
Europe:
5 Kelvin Park South, Kelvin South, East Kilbride, G75 ORH, United Kingdom • Tel: +44-870-870-8747 • Fax: +44-870-870-8757
Asia/Pacific:
Plot 18, Lrg Jelawat 4, Kawasan Perindustrian Seberang Jaya 13700, Prai, Penang, Malaysia • Tel: +604-3992909 • Fax: +604-3992903
4
SU564288FD8NZCU
May 30, 2007
Pin Description Table (Contd.)
Symbol
SA0~SA2
SDA
SCL
V
DD,
V
SS
V
REF
V
DDSPD
V
DDID
NC
DU
Type
LVTTL
LVTTL
LVTTL
Supply
Supply
Supply
Supply
-
-
Polarity
-
-
-
-
-
-
-
-
-
Function
These signals are tied on the system to either V
SS
or V
DD
to configure the serial SPD.
This bidirectional pin is used to transfer data into or out of the SPD EEPROM. A resistor
must be connected on the system board from the SDA bus line to V
DD
to act as a pullup.
This signal is used to clock data into and out of the SPD EEPROM. A resistor may be con-
nected on the system board from the SCL bus line to V
DD
to act as a pullup.
Power and ground for the DDR SDRAM input buffers and core logic.
Reference voltage for SSTL2 inputs.
Serial EEPROM positive power supply (wired to a separate power pin at the connector
which supports both 2.3 Volt and 3.3 Volt operation).
V
DD
Identification flag (not used).
No Connect.
Do Not Use.
Corporate Headquarters:
P. O. Box 1757, Fremont, CA 94538, USA • Tel:(510) 623-1231 • Fax:(510) 623-1434 • E-mail: info@smartm.com
Europe:
5 Kelvin Park South, Kelvin South, East Kilbride, G75 ORH, United Kingdom • Tel: +44-870-870-8747 • Fax: +44-870-870-8757
Asia/Pacific:
Plot 18, Lrg Jelawat 4, Kawasan Perindustrian Seberang Jaya 13700, Prai, Penang, Malaysia • Tel: +604-3992909 • Fax: +604-3992903
5
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