Am29LV040B
4 Megabit (512 K x 8-Bit)
CMOS 3.0 Volt-only, Uniform Sector 32-Pin Flash Memory
DISTINCTIVE CHARACTERISTICS
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Single power supply operation
— Full voltage range: 2.7 to 3.6 volt read and write
operations for battery-powered applications
— Regulated voltage range: 3.0 to 3.6 volt read and
write operations and for compatibility with high
performance 3.3 volt microprocessors
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Manufactured on 0.32 µm process technology
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High performance
— Full voltage range: access times as fast as 70 ns
— Regulated voltage range: access times as fast as
60 ns
s
Ultra low power consumption (typical values at
5 MHz)
— Automatic sleep mode: 1 µA
— Standby mode: 1 µA
— Read mode: 7 mA
— Program/erase mode: 15 mA
s
Flexible sector architecture
— Eight 64 Kbyte sectors
— Any combination of sectors can be erased;
supports full chip erase
— Sector Protection features:
Hardware method of locking a sector to prevent
any program or erase operations within that sector
Sectors can be locked via programming
equipment
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Unlock Bypass Program Command
— Reduces overall programming time when issuing
multiple program command sequences
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Embedded Algorithms
— Embedded Erase algorithms automatically
preprogram and erase the entire chip or any
combination of designated sectors
— Embedded Program algorithms automatically
writes and verifies data at specified addresses
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Minimum 1,000,000 write/erase cycles
guaranteed
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20-year data retention at 125°C
— Reliable operation for the life of the system
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Package option
— 32-pin PLCC
— 32-pin TSOP
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Compatibility with JEDEC standards
— Pinout and software compatible with single-
power supply Flash
— Superior inadvertent write protection
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Data# Polling and toggle bits
— Provides a software method of detecting program
or erase cycle completion
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Erase Suspend/Resume
— Supports reading data from or programming data
to a sector not being erased
Publication#
21354
Rev:
D
Amendment/0
Issue Date:
November 11, 1999
GENERAL DESCRIPTION
The Am29LV040B is a single power supply, 4 Mbit, 3.0
Volt-only Flash memory device organized as 524,288
bytes. The data appears on DQ0-DQ7. The device is
available in 32-pin PLCC and 32-pin TSOP packages. All
read, erase, and program operations are accomplished
using only a single power supply. The device can also be
programmed in standard EPROM programmers.
The device offers access times of 60, 70, 90, and 120 ns
allowing high speed microprocessors to operate without
wait states. To eliminate bus contention, the device has
separate control pins—chip enable (CE#), write enable
(WE#), and output enable (OE#)—to control normal
read and write operations.
The device requires only a
single power supply
(2.7 V–3.6V) for both read and write functions. Inter-
nally generated and regulated voltages are provided for
the program and erase operations.
The device is entirely command set compatible with the
JEDEC single-power-supply Flash standard.
Com-
mands are written to the command register using
standard microprocessor write timings. Register con-
tents serve as input to an internal state-machine that
controls the erase and programming circuitry. Write
cycles also internally latch addresses and data needed
for the programming and erase operations. Reading
data out of the device is similar to reading from other
Flash or EPROM devices.
Device programming occurs by executing the program
command sequence. This initiates the
Embedded
Program
algorithm—an internal algorithm that auto-
matically times the program pulse widths and verifies
proper cell margin. The
Unlock Bypass
mode facili-
tates faster programming times by requiring only two
write cycles to program data instead of four.
Device erasure occurs by executing the erase
command sequence. This initiates the
Embedded
Erase
algorithm—an internal algorithm that automatically
preprograms the array (if it is not already programmed)
before executing the erase operation. During erase, the
device automatically times the erase pulse widths and
verifies proper cell margin.
The host system can detect whether a program or
erase operation is complete by reading the DQ7 (Data#
Polling) and DQ6 (toggle)
status bits.
After a program
or erase cycle has been completed, the device is ready
to read array data or accept another command.
The
sector erase architecture
allows memory sectors
to be erased and reprogrammed without affecting the
data contents of other sectors. The device is fully
erased when shipped from the factory.
Hardware data protection
measures include a low
V
CC
detector that automatically inhibits write opera-
tions during power transitions. The
hardware sector
protection
feature disables both program and erase
operations in any combination of the sectors of
memory. This is achieved via programming equipment.
The
Erase Suspend
feature enables the user to put
erase on hold for any period of time to read data from,
or program data to, any sector that is not selected for
erasure. True background erase can thus be achieved.
The device offers two power-saving features. When
addresses have been stable for a specified amount of
time, the device enters the
automatic sleep mode.
The system can also place the device into the
standby
mode.
Power consumption is greatly reduced in both
these modes.
AMD’s Flash technology combines years of Flash
memory manufacturing experience to produce the
highest levels of quality, reliability and cost effectiveness.
The device electrically erases all bits within a sector
simultaneously via Fowler-Nordheim tunneling. The
data is programmed using hot electron injection.
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Am29LV040B
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