19-2216; Rev 0; 10/01
Low-Jitter, Low-Noise LVPECL-to-LVDS Level
Translator in an SC70 Package
General Description
The MAX9156 is an LVPECL-to-LVDS level translator
that accepts a single LVPECL input and translates it to
a single LVDS output. It is ideal for interfacing between
LVPECL and LVDS interfaces in systems that require
minimum jitter, noise, power, and space.
Ultra-low, 23ps
p-p
added deterministic jitter and
0.6ps
RMS
added random jitter ensure reliable commu-
nication in high-speed links that are highly sensitive to
timing errors, especially those incorporating clock-and-
data recovery, PLLs, serializers, or deserializers. The
MAX9156’s switching performance guarantees a
200Mbps data rate, but minimizes radiated noise by
guaranteeing 0.5ns minimum output transition time.
The MAX9156 operates from a single +3.3V supply and
consumes only 10mA supply current over a -40°C to
+85°C temperature range. It is available in a tiny 6-pin
SC70 package (half the size of a SOT23). Refer to the
MAX9155 data sheet for a low-jitter, low-noise LVDS
repeater in an SC70 package.
o
Tiny SC70 Package
o
Ultra-Low Jitter
23ps
p-p
Added Deterministic Jitter
(2
23
-1 PRBS)
0.6ps
RMS
Added Random Jitter
o
0.5ns (min) Transition Time Minimizes Radiated
Noise
o
200Mbps Guaranteed Data Rate
o
Low 10mA Supply Current
o
Output Conforms to ANSI/EIA/TIA-644 LVDS
Standard
o
High-Impedance Inputs and Outputs in
Power-Down Mode
Features
MAX9156
Applications
Digital Cross-Connects
Add/Drop Muxes
Network Switches/Routers
Cellular Phone Base Stations
DSLAMs
Multidrop Buses
PART
MAX9156EXT-T
Ordering Information
TEMP. RANGE
-40°C to +85°C
PIN-
PACKAGE
6 SC70-6
TOP
MARK
ABD
Pin Configuration
Typical Operating Circuit
V
CC
3.3V
MAX9156
OUT+
IN+
LVPECL
DRIVER
IN-
IN- 3
GND
4
IN+
OUT-
LVDS
SIGNALS
GND 2
5
V
CC
OUT- 1
TOP VIEW
MAX9156
6
OUT+
SC70
________________________________________________________________
Maxim Integrated Products
1
For pricing, delivery, and ordering information, please contact Maxim/Dallas Direct! at
1-888-629-4642, or visit Maxim’s website at www.maxim-ic.com.
Low-Jitter, Low-Noise LVPECL-to-LVDS Level
Translator in an SC70 Package
MAX9156
ABSOLUTE MAXIMUM RATINGS
V
CC
to GND ...........................................................-0.3V to +4.0V
IN+, IN- to GND.....................................................-0.3V to +4.0V
OUT+, OUT- to GND .............................................-0.3V to +4.0V
Short-Circuit Duration (OUT+, OUT-) .........................Continuous
Continuous Power Dissipation (T
A
= +70°C)
6-Pin SC70 (derate 3.1mW/°C above +70°C) ..............245mW
Storage Temperature Range .............................-65°C to +150°C
Junction Temperature ......................................................+150°C
Operating Temperature Range ...........................-40°C to +85°C
ESD Protection
Human Body Model, IN+, IN-, OUT+, OUT- ....................±8kV
Lead Temperature (soldering, 10s) .................................+300°C
Stresses beyond those listed under “Absolute Maximum Ratings” may cause permanent damage to the device. These are stress ratings only, and functional
operation of the device at these or any other conditions beyond those indicated in the operational sections of the specifications is not implied. Exposure to
absolute maximum rating conditions for extended periods may affect device reliability.
DC ELECTRICAL CHARACTERISTICS
(V
CC
= +3.0V to +3.6V, R
L
= 100Ω ±1%,
|
V
ID
|
= 0.05V to V
CC
, V
CM
=
|
V
ID
/ 2
|
to V
CC
-
|
V
ID
/ 2
|
, T
A
= -40°C to +85°C, unless otherwise
noted. Typical values at V
CC
= +3.3V, T
A
= +25°C.) (Notes 1, 2)
PARAMETER
LVPECL INPUT
Differential Input High Threshold
Differential Input Low Threshold
Input Resistor
Input Current
Power-Off Input Current
LVDS OUTPUT
Differential Output Voltage
Differential Output Voltage
Offset (Common-Mode) Voltage
Change in V
OS
for
Complementary Output States
Output High Voltage
Output Low Voltage
Differential Output Voltage
Power-Off Output Leakage
Current
Differential Output Resistance
Output Short Current
POWER SUPPLY
Supply Current
I
CC
10
15
mA
V
OD
∆V
OD
V
OS
∆V
OS
V
OH
V
OL
V
OD+
IO
OFF
RO
DIFF
I
SC
IN+, IN- open
V
CC
= 0
OUT+ = 3.6V, other output open
OUT- = 3.6V, other output open
0.9
+250
-10
-10
100
Figure 2
Figure 2
Figure 2
Figure 2
1.125
250
360
0.008
1.25
0.005
1.44
1.08
+360
0.02
0.02
260
-5
-5
+450
10
10
400
-15
-15
450
25
1.375
25
1.6
mV
mV
V
mV
V
V
mV
µA
Ω
mA
V
TH
V
TL
R
IN
I
IN+
, I
IN-
I
IN+
, I
IN-
Figure 1
IN+ = 3.6V, IN- = 0
IN+ = 0, IN- = 3.6V
V
CC
= 0,
Figure 1
IN+ = 3.6V, IN- = 0
IN+ = 0, IN- = 3.6V
-50
360
-10
-10
-10
-10
7
-7
1328
2.7
2.7
2.7
2.7
10
10
10
10
50
mV
mV
kΩ
µA
µA
SYMBOL
CONDITIONS
MIN
TYP
MAX
UNITS
V
CC
= +3.6V or 0
V
ID
= +50mV, OUT+ = GND
V
ID
= -50mV, OUT- = GND
2
_______________________________________________________________________________________
Low-Jitter, Low-Noise LVPECL-to-LVDS Level
Translator in an SC70 Package
AC ELECTRICAL CHARACTERISTICS
(V
CC
= +3.0V to +3.6V, R
L
= 100Ω ±1%, C
L
= 10pF,
|
V
ID
|
= 0.15V to V
CC
, V
CM
=
|
V
ID
/ 2
|
to V
CC
-
|
V
ID
/ 2
|
, T
A
= -40°C to +85°C, unless
otherwise noted. Typical values at V
CC
= +3.3V, T
A
= +25°C.) (Notes 3, 4, 5) (Figures 3, 4)
PARAMETER
Differential Propagation Delay High
to Low
Differential Propagation Delay Low to
High
Added Deterministic Jitter
(Notes 6, 11)
Added Random Jitter (Notes 7, 11)
Differential Part-to-Part Skew (Note 8)
Differential Part-to-Part Skew (Note 9)
Switching Supply Current
Rise Time
Fall Time
Input Frequency (Note 10)
SYMBOL
t
PHLD
t
PLHD
t
DJ
t
RJ
t
SKPP1
t
SKPP2
I
CCSW
t
TLH
t
THL
f
MAX
0.5
0.5
100
11.3
0.66
0.64
200Mbps 2
23
-1 PRBS data pattern
f
IN
= 100MHz
CONDITIONS
MIN
1.3
1.3
TYP
2.0
2.0
23
0.6
0.17
MAX
2.8
2.8
100
2.9
0.6
1.5
18
1.0
1.0
UNITS
ns
ns
ps
p-p
ps
RMS
ns
ns
mA
ns
ns
MHz
MAX9156
Note 1:
All devices are 100% tested at T
A
= +25°C. Limits over temperature are guaranteed by design and characterization.
Note 2:
Current into a pin is defined as positive. Current out of a pin is defined as negative. All voltages are referenced to ground
except V
TH
, V
TL
, V
OD
, and
∆V
OD
.
Note 3:
Guaranteed by design and characterization.
Note 4:
Signal generator output (unless otherwise noted): frequency = 100MHz, 50% duty cycle, R
O
= 50Ω, t
R
= 1.5ns, and t
F
=
1.5ns (0% to 100%).
Note 5:
C
L
includes scope probe and test jig capacitance.
Note 6:
Signal generator output for t
DJ
: V
OD
= 150mV, V
OS
= 1.2V, t
DJ
includes pulse (duty cycle) skew.
Note 7:
Signal generator output for t
RJ
: V
OD
= 150mV, V
OS
= 1.2V.
Note 8:
t
SKPP1
is the magnitude difference of any differential propagation delays between devices operating over rated conditions
at the same supply voltage, input common-mode voltage, and ambient temperature.
Note 9:
t
SKPP2
is the magnitude difference of any differential propagation delays between devices operating over rated conditions.
Note 10:
Device meets V
OD
DC specification and AC specifications while operating at f
MAX
.
Note 11:
Jitter added to the input signal.
_______________________________________________________________________________________
3
Low-Jitter, Low-Noise LVPECL-to-LVDS Level
Translator in an SC70 Package
MAX9156
Typical Operating Characteristics
(V
CC
= +3.3V, R
L
= 100Ω ±1%, C
L
= 10pF,
|
V
ID
|
= 0.2V, V
CM
= 1.2V, T
A
= +25°C, unless otherwise noted. Signal generator output:
frequency = 100MHz, 50% duty cycle, R
O
= 50Ω, t
R
= 1.5ns, and t
F
= 1.5ns (0% to 100%), unless otherwise noted.)
SUPPLY CURRENT
VS.
INPUT FREQUENCY
MAX9156 toc01
SWITCHING SUPPLY CURRENT
VS.
TEMPERATURE
MAX9156 toc02
OUTPUT SHORT-CIRCUIT CURRENT
VS.
SUPPLY VOLTAGE
OUTPUT SHORT-CIRCUIT CURRENT (mA)
MAX9156 toc03
21
18
SUPPLY CURRRENT (mA)
15
12
9
6
3
0
0
12.00
11.75
SUPPLY CURRENT (mA)
11.50
11.25
11.00
10.75
10.50
10.25
10.00
5.10
5.09
5.08
5.07
5.06
5.05
-40
-15
10
35
60
85
3.0
3.1
3.2
3.3
3.4
3.5
3.6
TEMPERATURE (°C)
SUPPLY VOLTAGE (V)
25 50 75 100 125 150 175 200 225 250
INPUT FREQUENCY (MHz)
OUTPUT LOW VOLTAGE
VS.
SUPPLY VOLTAGE
MAX9156 toc04
OUTPUT HIGH VOLTAGE
VS.
SUPPLY VOLTAGE
MAX9156 toc05
DIFFERENTIAL PROPAGATION DELAY
VS.
SUPPLY VOLTAGE
DIFFERENTIAL PROPAGATION DELAY (ns)
MAX9156 toc06
1.12
1.11
OUTPUT LOW VOLTAGE (V)
1.10
1.09
1.08
1.07
1.06
1.05
3.0
3.1
3.2
3.3
3.4
3.5
1.550
1.525
OUTPUT HIGH VOLTAGE (V)
1.500
1.475
1.450
1.425
1.400
1.375
1.350
2.1
t
PHLD
2.0
1.9
t
PLHD
1.8
1.7
3.0
3.1
3.2
3.3
3.4
3.5
3.6
3.0
3.1
3.2
3.3
3.4
3.5
3.6
SUPPLY VOLTAGE (V)
SUPPLY VOLTAGE (V)
3.6
SUPPLY VOLTAGE (V)
DIFFERENTIAL PROPAGATION DELAY
VS.
TEMPERATURE
MAX9156 toc07
TRANSITION TIME
VS.
SUPPLY VOLTAGE
t
THL
725
TRANSITION TIME (ps)
700
675
650
625
600
575
t
TLH
MAX9156 toc08
2.5
DIFFERENTIAL PROPAGATION DELAY (ns)
750
2.3
2.1
t
PHLD
1.9
t
PLHD
1.7
1.5
-40
-15
10
35
60
85
TEMPERATURE (°C)
550
3.0
3.1
3.2
3.3
3.4
3.5
3.6
SUPPLY VOLTAGE (V)
4
_______________________________________________________________________________________
Low-Jitter, Low-Noise LVPECL-to-LVDS Level
Translator in an SC70 Package
MAX9156
Typical Operating Characteristics (continued)
(V
CC
= +3.3V, R
L
= 100Ω ±1%, C
L
= 10pF,
|
V
ID
|
= 0.2V, V
CM
= 1.2V, T
A
= +25°C, unless otherwise noted. Signal generator output:
frequency = 100MHz, 50% duty cycle, R
O
= 50Ω, t
R
= 1.5ns, and t
F
= 1.5ns (0% to 100%), unless otherwise noted.)
TRANSITION TIME
VS.
TEMPERATURE
MAX9156 toc09
DIFFERENTIAL OUTPUT VOLTAGE
VS.
LOAD RESISTOR
DIFFERENTIAL OUTPUT VOLTAGE (mV)
MAX9156 toc10
800
750
TRANSITION TIME (ps)
700
650
600
550
500
450
400
-40
-15
10
35
60
t
TLH
, t
THL
600
500
400
300
200
100
0
85
25
50
75
100
125
150
TEMPERATURE (°C)
LOAD RESISTOR (Ω)
Pin Description
PIN
1
2
3
4
5
6
NAME
OUT-
GND
IN-
IN+
V
CC
OUT+
Ground
Inverting LVPECL-Compatible Input
Noninverting LVPECL-Compatible
Input
Power Supply. Bypass V
CC
to GND
with a 0.01µF ceramic capacitor.
Noninverting LVDS Output
FUNCTION
Inverting LVDS Output
Detailed Description
The LVDS interface standard is a signaling method
intended for point-to-point communication over a con-
trolled-impedance medium, as defined by the ANSI/
TIA/EIA-644 and IEEE 1596.3 standards. The LVDS
standard uses a lower voltage swing than other com-
mon communication standards, achieving higher data
rates with reduced power consumption while reducing
EMI emissions and system susceptibility to noise.
The MAX9156 is a 200Mbps LVDS translator intended
for high-speed, point-to-point, low-power applications.
The MAX9156 accepts differential LVPECL inputs and
produces an LVDS output. The input voltage range
includes signals from GND up to V
CC
, allowing interop-
eration with 3.3V LVPECL devices.
The MAX9156 provides a high output when the inputs
are open. See Table 1.
Table 1. Function Table (Figure 2)
INPUT, V
ID
> 50mV
< -50mV
50mV
>
V
ID
>
-50mV
Open
OUTPUT, V
OD
High
Low
Indeterminate
High
Note:
V
ID
= (IN+ - IN-), V
OD
= (OUT+ - OUT-)
High = 450mV
≥
V
OD
≥
250mV
Low = -250mV
≥
V
OD
≥
-450mV
_______________________________________________________________________________________
5
京公网安备 11010802033920号
Copyright © 2005-2026 EEWORLD.com.cn, Inc. All rights reserved
电子工程世界
