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AM42DL6404G85IS: 产品描述IC,MIXED MEMORY,FLASH+SRAM,CMOS,BGA,73PIN,PLASTIC; 产品类别存储存储; 文件大小1MB，共61页; 制造商Cypress(赛普拉斯)

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AM42DL6404G85IS概述

IC,MIXED MEMORY,FLASH+SRAM,CMOS,BGA,73PIN,PLASTIC

AM42DL6404G85IS规格参数

参数名称	属性值
是否Rohs认证	不符合
厂商名称	Cypress(赛普拉斯)
Reach Compliance Code	compliant
最长访问时间	85 ns
JESD-30 代码	R-PBGA-B73
内存集成电路类型	MEMORY CIRCUIT
混合内存类型	FLASH+SRAM
端子数量	73
最高工作温度	85 °C
最低工作温度	-40 °C
封装主体材料	PLASTIC/EPOXY
封装代码	FBGA
封装等效代码	BGA73,10X12,32
封装形状	RECTANGULAR
封装形式	GRID ARRAY, FINE PITCH
电源	3 V
认证状态	Not Qualified
最大压摆率	0.045 mA
标称供电电压 (Vsup)	3 V
表面贴装	YES
技术	CMOS
温度等级	INDUSTRIAL
端子形式	BALL
端子节距	0.8 mm
端子位置	BOTTOM
Base Number Matches	1

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Am42DL6404G

Data Sheet

July 2003

The following document specifies Spansion memory products that are now offered by both Advanced

Micro Devices and Fujitsu. Although the document is marked with the name of the company that orig-

inally developed the specification, these products will be offered to customers of both AMD and

Fujitsu.

Continuity of Specifications

There is no change to this datasheet as a result of offering the device as a Spansion product. Any

changes that have been made are the result of normal datasheet improvement and are noted in the

document revision summary, where supported. Future routine revisions will occur when appropriate,

and changes will be noted in a revision summary.

Continuity of Ordering Part Numbers

AMD and Fujitsu continue to support existing part numbers beginning with “Am” and “MBM”. To order

these products, please use only the Ordering Part Numbers listed in this document.

For More Information

Please contact your local AMD or Fujitsu sales office for additional information about Spansion

memory solutions.

Publication Number

26092

Revision

Amendment

Issue Date

March 20, 2002

P R E L I M I N A R Y

TABLE OF CONTENTS

Product Selector Guide . . . . . . . . . . . . . . . . . . . . . 5

MCP Block Diagram. . . . . . . . . . . . . . . . . . . . . . . . 5

flash memory Block Diagram . . . . . . . . . . . . . . . . 6

Connection Diagram . . . . . . . . . . . . . . . . . . . . . . . . 7

Special Package Handling Instructions .................................... 7

Pin Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8

Logic Symbol . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8

Ordering Information . . . . . . . . . . . . . . . . . . . . . . . 9

MCP Device Bus Operations . . . . . . . . . . . . . . . . 10

Table 1. Device Bus Operations—Flash Word Mode, CIOf = V

... 10

Table 2. Device Bus Operations—Flash Byte Mode, CIOf = V

....11

Figure 4. Erase Operation.............................................................. 28

Table 12. Am29DL640G Command Definitions .............................. 29

Write Operation Status . . . . . . . . . . . . . . . . . . . . 30

DQ7: Data# Polling ................................................................. 30

Figure 5. Data# Polling Algorithm .................................................. 30

RY/BY#: Ready/Busy# ............................................................ 31

DQ6: Toggle Bit I .................................................................... 31

Figure 6. Toggle Bit Algorithm........................................................ 31

Flash Device Bus Operations . . . . . . . . . . . . . . . 12

Word/Byte Configuration ........................................................ 12

Flash Requirements for Reading Array Data .......................... 12

Writing Commands/Command Sequences ............................ 12

Accelerated Program Operation .......................................... 12

Autoselect Functions ........................................................... 12

Simultaneous Read/Write Operations with Zero Latency ....... 12

Standby Mode ........................................................................ 13

Automatic Sleep Mode ........................................................... 13

RESET#: Hardware Reset Pin ............................................... 13

Output Disable Mode .............................................................. 13

Table 3. Am29DL640G Sector Architecture ....................................14

Table 4. Bank Address ....................................................................17

Table 5. SecSi Sector Addresses ...............................................17

DQ2: Toggle Bit II ................................................................... 32

Reading Toggle Bits DQ6/DQ2 ............................................... 32

DQ5: Exceeded Timing Limits ................................................ 32

DQ3: Sector Erase Timer ....................................................... 32

Table 13. Write Operation Status ................................................... 33

Absolute Maximum Ratings . . . . . . . . . . . . . . . . 34

Figure 7. Maximum Negative Overshoot Waveform ...................... 34

Figure 8. Maximum Positive Overshoot Waveform........................ 34

Flash DC Characteristics . . . . . . . . . . . . . . . . . . 35

CMOS Compatible .................................................................. 35

Figure 9. I

CC1

Current vs. Time (Showing Active and

Automatic Sleep Currents) ............................................................. 37

Figure 10. Typical I

CC1

vs. Frequency............................................ 37

Test Conditions . . . . . . . . . . . . . . . . . . . . . . . . . . 38

Figure 11. Test Setup.................................................................... 38

Figure 12. Input Waveforms and Measurement Levels ................. 38

Sector/Sector Block Protection and Unprotection .................. 18

Table 6. Am29DL640G Boot Sector/Sector Block Addresses for Pro-

tection/Unprotection ........................................................................18

AC Characteristics . . . . . . . . . . . . . . . . . . . . . . . . 39

SRAM CE#s Timing ................................................................ 39

Figure 13. Timing Diagram for Alternating

Between SRAM to Flash ................................................................ 39

Write Protect (WP#) ................................................................ 19

Table 7. WP#/ACC Modes ..............................................................19

Flash AC Characteristics . . . . . . . . . . . . . . . . . . 40

Read-Only Operations ........................................................... 40

Figure 14. Read Operation Timings............................................... 40

Temporary Sector Unprotect .................................................. 19

Figure 1. Temporary Sector Unprotect Operation........................... 19

Figure 2. In-System Sector Protect/Unprotect Algorithms .............. 20

Hardware Reset (RESET#) .................................................... 41

Figure 15. Reset Timings ............................................................... 41

SecSi™ (Secured Silicon) Sector

Flash Memory Region ............................................................ 21

Hardware Data Protection ...................................................... 21

Low V

Write Inhibit ........................................................... 21

Write Pulse “Glitch” Protection ............................................ 22

Logical Inhibit ...................................................................... 22

Power-Up Write Inhibit ......................................................... 22

Common Flash Memory Interface (CFI) . . . . . . . 22

Table 8. CFI Query Identification String.......................................... 22

System Interface String................................................................... 23

Table 10. Device Geometry Definition ............................................ 23

Table 11. Primary Vendor-Specific Extended Query ...................... 24

Word/Byte Configuration (CIOf) .............................................. 42

Figure 16. CIOf Timings for Read Operations................................ 42

Figure 17. CIOf Timings for Write Operations................................ 42

Erase and Program Operations .............................................. 43

Figure 18. Program Operation Timings..........................................

Figure 19. Accelerated Program Timing Diagram..........................

Figure 20. Chip/Sector Erase Operation Timings ..........................

Figure 21. Back-to-back Read/Write Cycle Timings ......................

Figure 22. Data# Polling Timings (During Embedded Algorithms).

Figure 23. Toggle Bit Timings (During Embedded Algorithms)......

Figure 24. DQ2 vs. DQ6.................................................................

Temporary Sector Unprotect .................................................. 48

Figure 25. Temporary Sector Unprotect Timing Diagram .............. 48

Figure 26. Sector/Sector Block Protect and

Unprotect Timing Diagram ............................................................. 49

Flash Command Definitions . . . . . . . . . . . . . . . . 25

Reading Array Data ................................................................ 25

Reset Command ..................................................................... 25

Autoselect Command Sequence ............................................ 25

Enter SecSi™ Sector/Exit SecSi Sector Command Sequence ..

Byte/Word Program Command Sequence ............................. 26

Unlock Bypass Command Sequence .................................. 26

Figure 3. Program Operation .......................................................... 27

Alternate CE#f Controlled Erase and Program Operations .... 50

Figure 27. Flash Alternate CE#f Controlled Write (Erase/Program)

Operation Timings.......................................................................... 51

Read Cycle ............................................................................. 52

Figure 28. SRAM Read Cycle—Address Controlled...................... 52

Figure 29. SRAM Read Cycle ........................................................ 53

Write Cycle ............................................................................. 54

Figure 30. SRAM Write Cycle—WE# Control ................................ 54

Figure 31. SRAM Write Cycle—CE1#s Control ............................. 55

Figure 32. SRAM Write Cycle—UB#s and LB#s Control............... 56

Chip Erase Command Sequence ........................................... 27

Sector Erase Command Sequence ........................................ 27

Erase Suspend/Erase Resume Commands ........................... 28

Flash Erase And Programming Performance . . 57

March 20, 2002

Am42DL6404G

AM42DL6404G85IS相似产品对比

	AM42DL6404G85IS	AM42DL6404G70IS	AM42DL6404G85IT	AM42DL6404G70IT
描述	IC,MIXED MEMORY,FLASH+SRAM,CMOS,BGA,73PIN,PLASTIC	IC,MIXED MEMORY,FLASH+SRAM,CMOS,BGA,73PIN,PLASTIC	IC,MIXED MEMORY,FLASH+SRAM,CMOS,BGA,73PIN,PLASTIC	IC,MIXED MEMORY,FLASH+SRAM,CMOS,BGA,73PIN,PLASTIC
是否Rohs认证	不符合	不符合	不符合	不符合
厂商名称	Cypress(赛普拉斯)	Cypress(赛普拉斯)	Cypress(赛普拉斯)	Cypress(赛普拉斯)
Reach Compliance Code	compliant	compliant	compliant	compliant
最长访问时间	85 ns	70 ns	85 ns	70 ns
JESD-30 代码	R-PBGA-B73	R-PBGA-B73	R-PBGA-B73	R-PBGA-B73
内存集成电路类型	MEMORY CIRCUIT	MEMORY CIRCUIT	MEMORY CIRCUIT	MEMORY CIRCUIT
混合内存类型	FLASH+SRAM	FLASH+SRAM	FLASH+SRAM	FLASH+SRAM
端子数量	73	73	73	73
最高工作温度	85 °C	85 °C	85 °C	85 °C
最低工作温度	-40 °C	-40 °C	-40 °C	-40 °C
封装主体材料	PLASTIC/EPOXY	PLASTIC/EPOXY	PLASTIC/EPOXY	PLASTIC/EPOXY
封装代码	FBGA	FBGA	FBGA	FBGA
封装等效代码	BGA73,10X12,32	BGA73,10X12,32	BGA73,10X12,32	BGA73,10X12,32
封装形状	RECTANGULAR	RECTANGULAR	RECTANGULAR	RECTANGULAR
封装形式	GRID ARRAY, FINE PITCH	GRID ARRAY, FINE PITCH	GRID ARRAY, FINE PITCH	GRID ARRAY, FINE PITCH
电源	3 V	3 V	3 V	3 V
认证状态	Not Qualified	Not Qualified	Not Qualified	Not Qualified
最大压摆率	0.045 mA	0.045 mA	0.045 mA	0.045 mA
标称供电电压 (Vsup)	3 V	3 V	3 V	3 V
表面贴装	YES	YES	YES	YES
技术	CMOS	CMOS	CMOS	CMOS
温度等级	INDUSTRIAL	INDUSTRIAL	INDUSTRIAL	INDUSTRIAL
端子形式	BALL	BALL	BALL	BALL
端子节距	0.8 mm	0.8 mm	0.8 mm	0.8 mm
端子位置	BOTTOM	BOTTOM	BOTTOM	BOTTOM
Base Number Matches	1	1	1	1

AM42DL6404G85IS

AM42DL6404G85IS概述

AM42DL6404G85IS规格参数

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