HN29W51214S Series
512M AND type Flash Memory
More than 16,057-sector (271,299,072-bit)
×
2
ADE-203-1155C (Z)
Rev. 3.0
Mar. 8, 2001
Description
The Hitachi HN29W51214S Series is stacked 2 chips Hitachi 256-Mbit Flash memory (HN29W25611S) that
are CMOS Flash Memory with AND type memory cells. It has fully automatic programming and erase
capabilities with a single 3.3 V power supply. The functions are compatible with HN29W25611S Series and
controlled by simple external commands. To fit the I/O card applications, the unit of programming and erase
is as small as (2048 + 64) bytes. Initial available sectors of HN29W51214S are more than 32,114 (98% of all
sector address).
Features
•
On-board single power supply (V
CC
): V
CC
= 2.7 V to 3.6 V
•
Organization
AND Flash Memory: (2048 + 64) bytes
×
(More than 16,057 sectors)
×
2
Data register: (2048 + 64) bytes
×
2
•
Multi-level memory cell
2 bit/per memory cell
•
Automatic programming
Sector program time: 3.0 ms (typ)
System bus free
Address, data latch function
Internal automatic program verify function
Status data polling function
•
Automatic erase
Single sector erase time: 1.5 ms (typ)
System bus free
Internal automatic erase verify function
Status data polling function
HN29W51214S Series
•
Erase mode
Single sector erase ((2048 + 64) byte unit)
•
Fast serial read access time:
First access time: 50 µs (max)
Serial access time : 80 ns (max) (V
CC
= 2.7 V to 3.6 V)
: 60 ns (max) (V
CC
= 3.0 V to 3.6 V)
•
Low power dissipation:
I
CC2
= 50 mA (max) (Read) (1-chip operation)
I
CC2
= 100 mA (max) (Read) (2-chip operation)
I
SB2
= 50 µA (max) (Standby) (1-chip operation)
I
SB2
= 100 µA (max) (Standby) (2-chip operation)
I
CC3
/I
CC4
= 40 mA (max) (Erase/Program) (1-chip operation)
I
CC3
/I
CC4
= 80 mA (max) (Erase/Program) (2-chip operation)
I
SB3
= 5 µA (max) (Deep standby) (1-chip operation)
I
SB3
= 10 µA (max) (Deep standby) (2-chip operation)
•
The following architecture is required for data reliability.
Error correction: more than 3-bit error correction per each sector read
Spare sectors: 1.8% (290 sectors)/chip within usable sectors
Ordering Information
Type No.
HN29W51214ST-80
Available sector
More than 32,114 sectors
Package
12.0
×
18.40 mm
2
0.5 mm pitch
48-pin plastic TSOP I (TFP-48DA)
2
HN29W51214S Series
Pin Arrangement
48-pin TSOP
V
CC
*
1
V
SS
*
1
V
SS
*
1
V
SS
*
1
V
SS
*
1
RES*
1
RDY/Busy*
1
SC*
1
OE*
1
I/O0*
1
I/O1*
1
I/O2*
1
I/O3*
1
V
CC
*
1
V
SS
*
1
I/O4*
1
I/O5*
1
I/O6*
1
I/O7*
1
CDE*
1
WE*
1
CE*
1
V
SS
*
1
V
SS
*
1
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
(Top view)
48
47
46
45
44
43
42
41
40
39
38
37
36
35
34
33
32
31
30
29
28
27
26
25
V
CC
*
2
V
SS
*
2
V
SS
*
2
V
SS
*
2
V
SS
*
2
RES*
2
RDY/Busy*
2
SC*
2
OE*
2
I/O0*
2
I/O1*
2
I/O2*
2
I/O3*
2
V
CC
*
2
V
SS
*
2
I/O4*
2
I/O5*
2
I/O6*
2
I/O7*
2
CDE*
2
WE*
2
CE*
2
V
SS
*
2
V
SS
*
2
Notes: 1. Upper chip.
2. Lower chip.
Pin Description
Pin name
I/O0 to I/O7
CE
OE
WE
CDE
V
CC
V
SS
RDY/Busy
RES
SC
Function
Input/output
Chip enable
Output enable
Write enable
Command data enable
Power supply
Ground
Ready/Busy
Reset
Serial clock
3
HN29W51214S Series
Block Diagram
Upper pellet
2048 + 64
X-decoder
16384
×
(2048 + 64)
×
8
memory matrix
••
I/O0
to
I/O7
Data
input
buffer
Input
data
control
Data register (2048 + 64)
•
•
•
Multiplexer •
•
•
•
•
Y-gating
Y-decoder
Data
output
buffer
•••
RDY/Busy
••
Y-address
counter
V
CC
V
SS
CE
OE
WE
SC
RES
CDE
Lower pellet
2048 + 64
Control
signal
buffer
Read/Program/Erase control
X-decoder
16384
×
(2048 + 64)
×
8
memory matrix
••
I/O0
to
I/O7
Data
input
buffer
Input
data
control
Data register (2048 + 64)
•
•
•
Multiplexer •
•
•
•
•
Y-gating
Y-decoder
Data
output
buffer
•••
RDY/Busy
••
Y-address
counter
V
CC
V
SS
CE
OE
WE
SC
RES
CDE
Control
signal
buffer
Read/Program/Erase control
4
16057 - 16384
Sector
address
buffer
16057 - 16384
Sector
address
buffer
HN29W51214S Series
Memory Map and Address
Sector address
2048 bytes
3FFFH
3FFEH
3FFDH
2048 bytes
2048 bytes
64 bytes
64 bytes
64 bytes
2048 bytes
0002H
0001H
0000H
000H
2048 + 64 bytes
2048 bytes
2048 bytes
64 bytes
64 bytes
64 bytes
800H
83FH Column address
Control bytes
Cycles
SA (1):
SA (2):
Column address CA (1):
CA (2):
Address
Sector address
I/O0 I/O1 I/O2 I/O3
A0 A1 A2 A3
First cycle
Second cycle A8 A9 A10 A11
A0 A1 A2 A3
First cycle
Second cycle A8 A9 A10 A11
I/O4
A4
A12
A4
×
I/O5 I/O6 I/O7
A5 A6 A7
A13
×*
2
×
A5 A6 A7
×
×
×
Notes: 1. Some failed sectors may exist in the device. The failed sectors can be recognized
by reading the sector valid data written in a part of the column address 800 to 83F
(The specific address is TBD.). The sector valid data must be read and kept outside
of the sector before the sector erase. When the sector is programmed, the sector
valid data should be written back to the sector.
2. An
×
means "Don't care". The pin level can be set to either V
IL
or V
IH
, referred
to DC characteristics.
16057 - 16384 sectors *
1
5
京公网安备 11010802033920号
Copyright © 2005-2026 EEWORLD.com.cn, Inc. All rights reserved
电子工程世界
