ICS8430-62
500MHz, Crystal-to-3.3V, 2.5V
Differential LVPECL Frequency Synthesizer
DATASHEET
General Description
The ICS8430-62 is a general purpose, dual output
Crystal-to-3.3V, 2.5V Differential LVPECL High
HiPerClockS™
Frequency Synthesizer and a member of the
HiPerClockS™ family of High Performance Clock
Solutions from IDT. The ICS8430-62 has a selectable
REF_CLK or crystal inputs. The VCO operates at a frequency range
of 250MHz to 500MHz. The VCO frequency is programmed in steps
equal to the value of the input reference or crystal frequency. The
VCO and output frequency can be programmed using the serial or
parallel interfaces to the configuration logic. Frequency steps as
small as 1MHz can be achieved using a 16MHz crystal or REF_CLK.
Features
•
•
•
•
•
•
•
•
•
•
•
Dual differential 3.3V or 2.5V LVPECL outputs
Selectable crystal oscillator interface or LVCMOS/LVTTL
REF_CLK
Output frequency range: 20.83MHz to 500MHz
Crystal input frequency range: 14MHz to 27MHz
VCO range: 250MHz to 500MHz
Parallel or serial interface for programming counter
and output dividers
RMS period jitter: 5ps (maximum)
Cycle-to-cycle jitter: 35ps (maximum)
Full 3.3V or 3.3V core/2.5V output supply
0°C to 70°C ambient operating temperature
Available in both standard (RoHS 5) and lead-free (RoHS 6)
packages
ICS
Block Diagram
VCO_SEL
Pullup
XTAL_SEL
Pullup
Pin Assignment
VCO_SEL
nP_LOAD
M4
M3
M1
M0
M2
REF_CLK
Pulldown
0
OSC
XTAL_IN
XTAL_OUT
32 31 30 29 28 27 26 25
1
÷16
÷1
÷1.5
÷2
÷3
÷4
÷6
÷8
÷12
M5
M6
M7
M8
N0
N1
N2
FOUT0
nFOUT0
V
EE
1
2
3
4
5
6
7
8
9
TEST
XTAL_IN
24
23
22
21
20
19
18
17
10 11 12 13 14 15 16
FOUT0
nFOUT1
nFOUT0
V
CC
FOUT1
V
CCO
V
EE
XTAL_OUT
REF_CLK
XTAL_SEL
V
CCA
S_LOAD
S_DATA
S_CLOCK
MR
PLL
Phase Detector
MR
Pulldown
VCO
÷M
0
1
FOUT1
nFOUT1
S_LOAD
Pulldown
S_DATA
Pulldown
S_CLOCK
Pulldown
nP_LOAD
Pulldown
M0:M8
N0:N2
9
3
Configuration
Interface Logic
TEST
ICS8430-62
32 Lead LQFP
7mm x 7mm x 1.4mm package body
Y Package
Top View
ICS8430AY-62 REVISION A JULY 2, 2009
1
©2009 Integrated Device Technology, Inc.
ICS8430-62 Datasheet
500MHz CRYSTAL-TO-3.3V, 2.5V DIFFERENTIAL LVPECL FREQUENCY SYNTHESIZER
Functional Description
NOTE: The functional description that follows describes operation
using a 16MHz crystal. Valid PLL loop divider values for different
crystal or input frequencies are defined in the Input Frequency
Characteristics, Table 5, NOTE 1.
The ICS8430-62 features a fully integrated PLL and therefore
requires no external components for setting the loop bandwidth. A
parallel-resonant, fundamental crystal is used as the input to the
on-chip oscillator. The output of the oscillator is divided by 16 prior to
the phase detector. With a 16MHz crystal, this provides a 1MHz
reference frequency. The VCO of the PLL operates over a range of
250MHz to 500MHz. The output of the M divider is also applied to the
phase detector.
The phase detector and the M divider force the VCO output
frequency to be M times the reference frequency by adjusting the
VCO control voltage. Note that for some values of M (either too high
or too low), the PLL will not achieve lock. The output of the VCO is
scaled by a divider prior to being sent to each of the LVPECL output
buffers. The divider provides a 50% output duty cycle.
The programmable features of the ICS8430-62 support two input
modes to program the M divider and N output divider. The two input
operational modes are parallel and serial.
Figure 1
shows the timing
diagram for each mode. In parallel mode, the nP_LOAD input is
initially LOW. The data on inputs M0 through M8 and N0 through N2
is passed directly to the M divider and N output divider. On the
LOW-to-HIGH transition of the nP_LOAD input, the data is latched
and the M divider remains loaded until the next LOW transition on
nP_LOAD or until a serial event occurs. As a result, the M and N bits
can be hard-wired to set the M divider and N output divider to a
specific default state that will automatically occur during power-up.
The TEST output is LOW when operating in the parallel input mode.
The relationship between the VCO frequency, the crystal frequency
and the M divider is defined as follows:
fVCO = fXTAL x M
16
The M value and the required values of M0 through M8 are shown in
Table 3B, Programmable VCO Frequency Function Table. Valid M
values for which the PLL will achieve lock for a 16MHz reference are
defined as 250
≤
M
≤
500. The frequency out is defined as follows:
fout = fVCO = fXTAL x M
N
16
N
Serial operation occurs when nP_LOAD is HIGH and S_LOAD is
LOW. The shift register is loaded by sampling the S_DATA bits with
the rising edge of S_CLOCK. The contents of the shift register are
loaded into the M divider and N output divider when S_LOAD
transitions from LOW-to-HIGH. The M divide and N output divide
values are latched on the HIGH-to-LOW transition of S_LOAD. If
S_LOAD is held HIGH, data at the S_DATA input is passed directly to
the M divider and N output divider on each rising edge of S_CLOCK.
The serial mode can be used to program the M and N bits and test
bits T1 and T0. The internal registers T0 and T1 determine the state
of the TEST output as follows:
T1
0
0
1
1
T0
0
1
0
1
TEST Output
LOW
S_DATA, Shift Register Input
Output of M Divider
Do Not Use
S
ERIAL
L
OADING
S_CLOCK
S_DATA
t
T1
S
T0
H
N2
N1
N0
M8
M7
M6
M5
M4
M3
M2
M1
M0
t
S_LOAD
nP_LOAD
t
S
P
ARALLEL
L
OADING
M0:M8, N0:N2
nP_LOAD
t
S
M, N
t
H
S_LOAD
Time
Figure 1. Parallel & Serial Load Operations
ICS8430AY-62 REVISION A JULY 2, 2009
2
©2009 Integrated Device Technology, Inc.
ICS8430-62 Datasheet
500MHz CRYSTAL-TO-3.3V, 2.5V DIFFERENTIAL LVPECL FREQUENCY SYNTHESIZER
Table 1. Pin Descriptions
Number
1, 2, 28, 29,
30, 31, 32
3, 4
5, 7
6
8, 16
9
10
11, 12
13
14, 15
Name
M5, M6, M0, M1,
M2, M3, M4
M7, M8
N0, N2
N1
V
EE
TEST
V
CC
FOUT1, nFOUT1
V
CCO
FOUT0, nFOUT0
Input
Input
Input
Input
Power
Output
Power
Output
Power
Output
Type
Description
Pulldown M divider inputs. Data latched on LOW-to-HIGH transition of nP_LOAD input.
LVCMOS/LVTTL interface levels.
Pullup
Pulldown Determines output divider value as defined in Table 3C, Function Table.
LVCMOS/LVTTL interface levels.
Pullup
Negative supply pins.
Test output which is ACTIVE in the serial mode of operation.
Output driven LOW in parallel mode. LVCMOS/LVTTL interface levels.
Core supply pin.
Differential output pair for the synthesizer. LVPECL interface levels.
Output supply pin for LVPECL outputs.
Differential output pair for the synthesizer. LVPECL interface levels.
Active High Master Reset. When logic HIGH, the internal dividers are reset
causing the true outputs FOUTx to go low and the inverted outputs nFOUTx to
Pulldown go high. When Logic LOW, the internal dividers and the outputs are enabled.
Assertion of MR does not affect loaded M, N, and T values.
LVCMOS/LVTTL interface levels.
Pulldown
Pulldown
Pulldown
Clocks in serial data present at S_DATA input into the shift register on the
rising edge of S_CLOCK. LVCMOS/LVTTL interface levels.
Shift register serial input. Data sampled on the rising edge of S_CLOCK.
LVCMOS/LVTTL interface levels.
Controls transition of data from shift register into the dividers.
LVCMOS/LVTTL interface levels.
Analog supply pin.
Pullup
Selects between crystal oscillator or REF_CLK inputs as the PLL reference
source. Selects XTAL inputs when HIGH. Selects REF_CLK when LOW.
LVCMOS/LVTTL interface levels.
17
MR
Input
18
19
20
21
22
23
24,
25
26
S_CLOCK
S_DATA
S_LOAD
V
CCA
XTAL_SEL
REF_CLK
XTAL_OUT
XTAL_IN
nP_LOAD
Input
Input
Input
Power
Input
Input
Input
Pulldown Single-ended reference clock input. LVCMOS/LVTTL interface levels.
Crystal oscillator interface. XTAL_IN is the input, XTAL_OUT is the output.
Parallel load input. Determines when data present at M8:M0 is loaded into M
Pulldown divider, and when data present at N2:N0 sets the N output divider value.
LVCMOS/LVTTL interface levels.
Pullup
Determines whether synthesizer is in PLL or bypass mode. When LOW,
synthesizer is in bypass mode, when HIGH,synthesizer is in PLL mode.
LVCMOS/LVTTL interface levels.
Input
27
VCO_SEL
Input
NOTE:
Pullup and Pulldown
refer to internal input resistors. See Table 2,
Pin Characteristics,
for typical values.
Table 2. Pin Characteristics
Symbol
C
IN
R
PULLUP
R
PULLDOWN
Parameter
Input Capacitance
Input Pullup Resistor
Input Pulldown Resistor
Test Conditions
Minimum
Typical
4
51
51
Maximum
Units
pF
k
Ω
k
Ω
ICS8430AY-62 REVISION A JULY 2, 2009
3
©2009 Integrated Device Technology, Inc.
ICS8430-62 Datasheet
500MHz CRYSTAL-TO-3.3V, 2.5V DIFFERENTIAL LVPECL FREQUENCY SYNTHESIZER
Function Tables
Table 3A. Parallel and Serial Mode Function Table
Inputs
MR
H
L
L
L
L
L
L
L
nP_LOAD
X
L
↑
H
H
H
H
H
M
X
Data
Data
X
X
X
X
X
N
X
Data
Data
X
X
X
X
X
S_LOAD
X
X
L
L
↑
↓
L
H
S_CLOCK
X
X
X
↑
L
L
X
↑
S_DATA
X
X
X
Data
Data
Data
X
Data
Conditions
Reset. Forces true outputs LOW.
Data on M and N inputs passed directly to the M divider
and N output divider. TEST output forced LOW.
Data is latched into input registers and remains loaded
until next LOW transition or until a serial event occurs.
Serial input mode. Shift register is loaded with data on
S_DATA on each rising edge of S_CLOCK.
Contents of the shift register are passed to the
M divider and N output divider.
M divider and N output divider values are latched.
Parallel or serial input do not affect shift registers.
S_DATA passed directly to M divider as it is clocked.
NOTE: L = LOW
H = HIGH
X = Don’t care
↑
= Rising edge transition
↓
= Falling edge transition
Table 3B. Programmable VCO Frequency Function Table
VCO Frequency
(MHz)
250
251
252
253
•
•
498
499
500
256
M Divide
250
251
252
253
•
•
498
499
500
M8
0
0
0
0
•
•
1
1
1
128
M7
1
1
1
1
•
•
1
1
1
64
M6
1
1
1
1
•
•
1
1
1
32
M5
1
1
1
1
•
•
1
1
1
16
M4
1
1
1
1
•
•
1
1
1
8
M3
1
1
1
1
•
•
0
0
0
4
M2
0
0
1
1
•
•
0
0
1
2
M1
1
1
0
0
•
•
1
1
0
1
M0
0
1
0
1
•
•
0
1
0
NOTE 1: These M divide values and the resulting frequencies correspond to a REF_CLK or crystal frequency of 16MHz.
ICS8430AY-62 REVISION A JULY 2, 2009
4
©2009 Integrated Device Technology, Inc.
ICS8430-62 Datasheet
500MHz CRYSTAL-TO-3.3V, 2.5V DIFFERENTIAL LVPECL FREQUENCY SYNTHESIZER
Table 3C. Programmable Output Divider Function Table
Inputs
N2
0
0
0
0
1
1
1
1
N1
0
0
1
1
0
0
1
1
N0
0
1
0
1
0
1
0
1
N Divider Value
1
1.5
2
3
4
6
8
12
Output Frequency (MHz)
Minimum
250
166.66
125
83.33
62.5
41.66
31.25
20.83
Maximum
500
333.33
250
166.66
125
83.33
62.5
41.66
Absolute Maximum Ratings
NOTE: Stresses beyond those listed under
Absolute Maximum Ratings
may cause permanent damage to the device.
These ratings are stress specifications only. Functional operation of product at these conditions or any conditions beyond
those listed in the
DC Characteristics or AC Characteristics
is not implied. Exposure to absolute maximum rating conditions for
extended periods may affect product reliability.
Item
Supply Voltage, V
CC
Inputs, V
I
Outputs, I
O
Continuous Current
Surge Current
Package Thermal Impedance,
θ
JA
Storage Temperature, T
STG
Rating
4.6V
-0.5V to V
CC
+ 0.5V
50mA
100mA
65.7°C/W (0 mps)
-65°C to 150°C
DC Electrical Characteristics
Table 4A. Power Supply DC Characteristics,
V
CC
= 3.3V±5%, V
CCO
= 3.3V±5% or 2.5V±5%, T
A
= 0°C to 70°C
Symbol
V
CC
V
CCA
V
CCO
I
EE
I
CCA
Parameter
Core Supply Voltage
Analog Supply Voltage
Output Supply Voltage
2.375
Power Supply Current
Analog Supply Current
2.5
2.625
130
14
V
mA
mA
Test Conditions
Minimum
3.135
V
CC
– 0.14
3.135
Typical
3.3
3.3
3.3
Maximum
3.465
V
CC
3.465
Units
V
V
V
ICS8430AY-62 REVISION A JULY 2, 2009
5
©2009 Integrated Device Technology, Inc.
聊聊、笑笑、闹闹
京公网安备 11010802033920号
Copyright © 2005-2026 EEWORLD.com.cn, Inc. All rights reserved
电子工程世界
