ADVANCE INFORMATION
Am29SL400C
4 Megabit (512 K x 8-Bit/256 K x 16-Bit)CMOS 1.8 Volt-only
Super Low Voltage Flash Memory
DISTINCTIVE CHARACTERISTICS
■
Single power supply operation
— 1.65 to 2.2 V for read, program, and erase
operations
— Ideal for battery-powered applications
■
Manufactured on 0.32 µm process technology
■
High performance
— Access times as fast as 100 ns
■
Ultra low power consumption (typical values at
5 MHz)
— 1 µA Automatic Sleep Mode current
— 1 µA standby mode current
— 5 mA read current
— 20 mA program/erase current
■
Flexible sector architecture
— One 16 Kbyte, two 8 Kbyte, one 32 Kbyte, and
seven 64 Kbyte sectors (byte mode)
— One 8 Kword, two 4 Kword, one 16 Kword, and
seven 32 Kword sectors (word mode)
— Supports full chip erase
— Sector Protection features:
A hardware method of locking a sector to
prevent any program or erase operations within
that sector
Sectors can be locked in-system or via
programming equipment
Temporary Sector Unprotect feature allows code
changes in previously locked sectors
■
Unlock Bypass Program Command
— Reduces overall programming time when
issuing multiple program command sequences
■
Top or bottom boot block configurations
available
■
Embedded Algorithms
— Embedded Erase algorithm automatically
preprograms and erases the entire chip or any
combination of designated sectors
— Embedded Program algorithm automatically
writes and verifies data at specified addresses
■
Minimum 1,000,000 erase cycle guarantee per
sector
■
20-year data retention at 125°C
■
Package option
— 48-ball FBGA
— 48-pin TSOP
■
Compatibility with JEDEC standards
— Pinout and software compatible with
single-power supply Flash
— Superior inadvertent write protection
■
Data# Polling and toggle bits
— Provides a software method of detecting
program or erase operation completion
■
Ready/Busy# pin (RY/BY#)
— Provides a hardware method of detecting
program or erase cycle completion
■
Erase Suspend/Erase Resume
— Suspends an erase operation to read data from,
or program data to, a sector that is not being
erased, then resumes the erase operation
■
Hardware reset pin (RESET#)
— Hardware method to reset the device to reading
array data
This document contains information on a product under development at Advanced Micro Devices. The information
is intended to help you evaluate this product. AMD reserves the right to change or discontinue work on this proposed
product without notice.
Publication#
26722
Rev:
A
Amendment+2
Issue Date:
February 5, 2003
Refer to AMD’s Website (www.amd.com) for the latest information.
A D V A N C E
I N F O R M A T I O N
GENERAL DESCRIPTION
The Am29SL400C is an 4Mbit, 1.8 V volt-only Flash
memory organized as 524,288 bytes or 262,144 words.
The device is offered in 48-pin TSOP and 48-ball
FBGA packages. The word-wide data (x16) appears on
DQ15–DQ0; the byte-wide (x8) data appears on
DQ7–DQ0. This device is designed to be programmed
and erased in-system with a single 1.8 volt V
CC
supply.
No V
PP
is for write or erase operations. The device can
also be programmed in standard EPROM program-
mers.
The standard device offers access times of 100, 120,
and 150 ns, allowing high speed microprocessors to
operate without wait states. To eliminate bus conten-
tion the device has separate chip enable (CE#), write
enable (WE#) and output enable (OE#) controls.
The device requires only a
single 1.8 volt power
supply
for both read and write functions. Internally
generated and regulated voltages are provided for the
program and erase operations.
The device is entirely command set compatible with the
JEDEC single-power-supply Flash standard.
Com-
mands are written to the command register using stan-
dard microprocessor write timings. Register contents
serve as input to an internal state-machine that con-
trols the erase and programming circuitry. Write cycles
also internally latch addresses and data needed for the
programming and erase operations. Reading data out
of the device is similar to reading from other Flash or
EPROM devices.
Device programming occurs by executing the program
command sequence. This initiates the
Embedded
Program
algorithm—an internal algorithm that auto-
matically times the program pulse widths and verifies
proper cell margin. The
Unlock Bypass
mode facili-
tates faster programming times by requiring only two
write cycles to program data instead of four.
Device erasure occurs by executing the erase
command sequence. This initiates the
Embedded
Erase
algorithm—an internal algorithm that automati-
cally preprograms the array (if it is not already pro-
grammed) before executing the erase operation.
During erase, the device automatically times the erase
pulse widths and verifies proper cell margin.
The host system can detect whether a program or
erase operation is complete by observing the RY/BY#
pin, or by reading the DQ7 (Data# Polling) and DQ6
(toggle)
status bits.
After a program or erase cycle
has been completed, the device is ready to read array
data or accept another command.
The
sector erase architecture
allows memory sectors
to be erased and reprogrammed without affecting the
data contents of other sectors. The device is fully
erased when shipped from the factory.
Hardware data protection
measures include a low
V
CC
detector that automatically inhibits write opera-
tions during power transitions. The
hardware sector
protection
feature disables both program and erase
operations in any combination of the sectors of
memory. This can be achieved in-system or via pro-
gramming equipment.
The
Erase Suspend
feature enables the user to put
erase on hold for any period of time to read data from,
or program data to, any sector that is not selected for
erasure. True background erase can thus be achieved.
The
hardware RESET# pin
terminates any operation
in progress and resets the internal state machine to
reading array data. The RESET# pin may be tied to the
system reset circuitry. A system reset would thus also
reset the device, enabling the system microprocessor
to read the boot-up firmware from the Flash memory.
The device offers two power-saving features. When
addresses have been stable for a specified amount of
time, the device enters the
automatic sleep mode.
The system can also place the device into the
standby
mode.
Power consumption is greatly reduced in both
these modes.
AMD’s Flash technology combines years of Flash
memory manufacturing experience to produce the
highest levels of quality, reliability and cost effective-
ness. The device electrically erases all bits within a
sector simultaneously via Fowler-Nordheim tunneling.
The data is programmed using hot electron injection.
2
Am29SL400C
February 5, 2003
A D V A N C E
I N F O R M A T I O N
TABLE OF CONTENTS
Product Selector Guide . . . . . . . . . . . . . . . . . . . . . 4
Block Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4
Special Handling Instructions for FBGA Packages .................. 6
Pin Configuration . . . . . . . . . . . . . . . . . . . . . . . . . . 7
Logic Symbol . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7
Ordering Information . . . . . . . . . . . . . . . . . . . . . . . 8
Device Bus Operations . . . . . . . . . . . . . . . . . . . . . . 9
Table 1. Am29SL400C Device Bus Operations ................................9
Figure 5. Toggle Bit Algorithm........................................................ 22
DQ5: Exceeded Timing Limits ................................................ 22
DQ3: Sector Erase Timer ....................................................... 22
Table 6. Write Operation Status ..................................................... 23
Absolute Maximum Ratings . . . . . . . . . . . . . . . . 24
Figure 6. Maximum Negative Overshoot Waveform ...................... 24
Figure 7. Maximum Positive Overshoot Waveform........................ 24
Word/Byte Configuration .......................................................... 9
Requirements for Reading Array Data ..................................... 9
Writing Commands/Command Sequences ............................ 10
Program and Erase Operation Status .................................... 10
Standby Mode ........................................................................ 10
Automatic Sleep Mode ........................................................... 10
RESET#: Hardware Reset Pin ............................................... 10
Output Disable Mode .............................................................. 11
Table 2. Am29SL400CT Top Boot Block Sector Address Table .....11
Table 3. Am29SL400CB Bottom Boot Block Sector Address Table 12
Operating Ranges . . . . . . . . . . . . . . . . . . . . . . . . . 24
DC Characteristics . . . . . . . . . . . . . . . . . . . . . . . . 25
Figure 8. I
CC1
Current vs. Time (Showing Active and Automatic
Sleep Currents) .............................................................................. 26
Figure 9. Typical I
CC1
vs. Frequency ............................................. 26
Test Conditions. . . . . . . . . . . . . . . . . . . . . . . . . . . 27
Figure 10. Test Setup..................................................................... 27
Table 7. Test Specifications ........................................................... 27
Key to Switching Waveforms .................................................. 27
Figure 11. Input Waveforms and Measurement Levels ................. 27
Autoselect Mode ..................................................................... 12
Table 4. Am29SL400C Autoselect Codes (High Voltage Method) ..13
AC Characteristics . . . . . . . . . . . . . . . . . . . . . . . . 28
Read Operations .................................................................... 28
Figure 12. Read Operations Timings ............................................. 28
Figure 13. RESET# Timings .......................................................... 29
Sector Protection/Unprotection ............................................... 13
Temporary Sector Unprotect .................................................. 13
Figure 1. In-System Sector Protect/Unprotect Algorithms .............. 14
Figure 1. Temporary Sector Unprotect Operation........................... 15
Word/Byte Configuration (BYTE#) ........................................ 30
Figure 14. BYTE# Timings for Read Operations............................ 30
Figure 15. BYTE# Timings for Write Operations............................ 30
Hardware Data Protection ...................................................... 15
Low V
CC
Write Inhibit .............................................................. 15
Write Pulse “Glitch” Protection ............................................... 15
Logical Inhibit .......................................................................... 15
Power-Up Write Inhibit ............................................................ 15
Command Definitions . . . . . . . . . . . . . . . . . . . . . 15
Reading Array Data ................................................................ 15
Reset Command ..................................................................... 15
Autoselect Command Sequence ............................................ 16
Word/Byte Program Command Sequence ............................. 16
Unlock Bypass Command Sequence ..................................... 16
Figure 2. Program Operation .......................................................... 17
Erase/Program Operations ..................................................... 31
Figure 16. Program Operation Timings.......................................... 32
Figure 17. Chip/Sector Erase Operation Timings .......................... 33
AC Characteristics
. . . . . . . . . . . . . . . . . . . . . . 34
Figure 18. Data# Polling Timings (During Embedded Algorithms). 34
Figure 19. Toggle Bit Timings (During Embedded Algorithms)...... 34
Figure 20. DQ2 vs. DQ6................................................................. 35
Temporary Sector Unprotect .................................................. 35
Figure 21. Temporary Sector Unprotect Timing Diagram .............. 35
Figure 22. Sector Protect/Unprotect Timing Diagram .................... 36
Alternate CE# Controlled Erase/Program Operations ............ 37
AC Characteristics . . . . . . . . . . . . . . . . . . . . . . . . 38
Figure 23. Alternate CE# Controlled Write Operation Timings ...... 38
Chip Erase Command Sequence ........................................... 17
Sector Erase Command Sequence ........................................ 17
Figure 3. Erase Operation............................................................... 18
Table 5. Am29SL400C Command Definitions ................................19
Write Operation Status ........................................................... 20
DQ7: Data# Polling ................................................................. 20
Figure 4. Data# Polling Algorithm ................................................... 20
RY/BY#: Ready/Busy# ........................................................... 20
DQ6: Toggle Bit I .................................................................... 21
DQ2: Toggle Bit II ................................................................... 21
Reading Toggle Bits DQ6/DQ2 .............................................. 21
Erase and Programming Performance . . . . . . . 39
Latchup Characteristics . . . . . . . . . . . . . . . . . . . . 39
TSOP Pin and BGA Package Capacitance . . . . . 39
Data Retention. . . . . . . . . . . . . . . . . . . . . . . . . . . . 39
Physical Dimensions . . . . . . . . . . . . . . . . . . . . . . 40
TSR048—48-Pin Reverse TSOP ........................................... 40
Physical Dimensions . . . . . . . . . . . . . . . . . . . . . . 41
FBA048—48-Ball Fine-Pitch Ball Grid Array (FBGA) 6 x 8 mm
Package .................................................................................. 41
Revision Summary . . . . . . . . . . . . . . . . . . . . . . . . 42
February 5, 2003
Am29SL400C
3
A D V A N C E
I N F O R M A T I O N
PRODUCT SELECTOR GUIDE
Family Part Number
Speed Options
Regulated Voltage Range V
CC
= 1.7–2.2 V
Standard Voltage Range V
CC
= 1.65–2.2 V
Max access time, ns (t
ACC
)
Max CE# access time, ns (t
CE
)
Max OE# access time, ns (t
OE
)
Note:
See “AC Characteristics” for full specifications.
100
100
35
-100R
-110
110
110
45
-120
120
120
50
-150
150
150
65
Am29SL400C
BLOCK DIAGRAM
RY/BY#
V
CC
V
SS
Sector Switches
Erase Voltage
Generator
Input/Output
Buffers
DQ0–DQ15 (A-1)
RESET#
WE#
BYTE#
State
Control
Command
Register
PGM Voltage
Generator
Chip Enable
Output Enable
Logic
STB
Data
Latch
CE#
OE#
STB
V
CC
Detector
Timer
Address Latch
Y-Decoder
Y-Gating
X-Decoder
Cell Matrix
A0–A17
4
Am29SL400C
February 5, 2003
A D V A N C E
I N F O R M A T I O N
CONNECTION DIAGRAMS
A15
A14
A13
A12
A11
A10
A9
A8
NC
NC
WE#
RESET#
NC
NC
RY/BY#
NC
A17
A7
A6
A5
A4
A3
A2
A1
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
Standard TSOP
48
47
46
45
44
43
42
41
40
39
38
37
36
35
34
33
32
31
30
29
28
27
26
25
A16
BYTE#
V
SS
DQ15/A-1
DQ7
DQ14
DQ6
DQ13
DQ5
DQ12
DQ4
V
CC
DQ11
DQ3
DQ10
DQ2
DQ9
DQ1
DQ8
DQ0
OE#
V
SS
CE#
A0
February 5, 2003
Am29SL400C
5
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