73M2901CL
V.22bis Single Chip Modem
DATA SHEET
JULY 2005
DESCRIPTION
The 73M2901CL is a single-chip modem that
combines all the controller (DTE) and data pump
functions necessary to implement an intelligent
V.22bis data modem.
It is suited for embedded applications where a data
return channel is needed through the telephone
network such as Set top Box, Point of Sale Terminal,
Automatic
Teller
machine,
Hand
Held
Communication Device and Smart Card Reader.
This device is based on TERIDIAN Semiconductor’s
implementation of the industry standard 8032
microcontroller core with a proprietary Multiply/
ACcumulate (MAC) coprocessor; Sigma-Delta A/D
and D/A converters (CODEC); and an analog DAA
drivers. The ROM and RAM necessary to operate
the modem are contained on the device.
Additionally, the 73M2901CL provides an on-chip
oscillator and hybrid.
FEATURES
•
•
•
•
True one chip solution for embedded systems
Low power
As low as 9.5mA operating, with standby and
power down mode available
Power supply operation from 3.6V to 2.7V
Data speed:
V.22bis – 2400bps
V.22/Bell212 – 1200bps
V.21/Bell103 – 300bps
V.23 – 1200/75bps (with PAVI turnaround)
Bell202 – 1200bps
Bell202/V23 4-wire operations
International Call Progress support
FCC68, CTR21, JATE, etc.
Worldwide Caller ID capability
Type I and II support
EIA 716 compliant
DTMF generation and detection
On chip hybrid driver
Blacklisting capability
Line-In-Use and Parallel Pick-Up (911) detection
capability
Manufacturing Self Test capability
Packaging:
32 pin PLCC / 32 pin TQFP / 44 pin LQFP
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•
•
•
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BLOCK DIAGRAM
Page: 1 of 18
©
2005 TERIDIAN Semiconductor Corporation
Rev 2.0
73M2901CL
V.22bis Single Chip Modem
DATA SHEET
HARDWARE DESCRIPTION
The 73M2901CL is designed to operate from a +3.6
to +2.7 volt supply with low power consumption
(~30mW @ 3.0 volts). The modem supports
automatic standby idle mode. The modem will also
accept a request to power down from the DTE via
hardware control. No additional major components
are required to complete the modem core logic. The
modem provides direct firmware LED support via
port pins.
HARDWARE FEATURES
•
•
•
•
•
•
Fully self-contained. “AT” Command interpreter
and data pump
User pins available
Synchronous serial data I/O available
Asynchronous serial port
On-chip hybrid and line driver.
Autobaud capability from 300bps to 9600bps
but no clocks will be supplied to the CPU. Instruction
processing and activity on the internal busses is
halted. Normal operation is resumed when an
interruption such as assertion of
DTR
or
RING,
a
character is sent to the 73M2901CL TXD input, or a
reset occurs.
ANALOG LINE / HYBRID INTERFACE
The 73M2901CL provides a differential analog
output (TXAP and TXAN) and a single-ended analog
input (RXA) with internal A/D and D/A converters. A
driver is provided for an internal hybrid function.
The internal hybrid driver is capable of driving an
external load matching impedance and a line-
coupling transformer. The internal hybrid/line driver
senses the load and adapts itself to its requirements.
The 73M2901CL provides firmware control for a
hook relay driver (RELAY) as well as interrupt
support for a ring detect opto-coupler (RING).
INTERRUPT PINS
The external interrupt sources,
DTR
and
RING,
come from dedicated input pins of the same name.
DTR informs the 73M2901CL that the host has
requested the 73M2901CL perform a specific
function. The function of
DTR
can be changed by
“AT” commands (described in full in the TERIDIAN
73M2901CL User’s Guide).
RING is used to inform the 73M2901CL that the
external DAA circuitry has detected a ring signal.
In addition, sending any character on the TXD line
also generates an internal interrupt.
CRYSTAL OSCILLATOR
The TERIDIAN 73M2901CL single chip modem can
use an external 11.0592 MHz reference clock or can
generate a clock using only a crystal and two
capacitors. If an external clock is used, it should be
applied to OSCIN.
POWER SUPPLY
Power is supplied to the 73M2901CL via the VPD
and VPA pins. The 73M2901CL is designed for a
single +3.6 to +2.7 volt supply and for low power
consumption (~30mW @ 3.0 volts). Ground is
supplied to the 73M2901CL via VND and VNA pins.
The 73M2901CL has been designed with separated
analog and digital supplies to insure the best
performance of the part by using different filtered
power supplies. It is recommended that separate
locally bypassed traces be used to apply power to
the analog supply VPA and the digital supply VPD.
LOW POWER MODE
The TERIDIAN 73M2901CL supports a low power
standby mode. If the low power standby option is
enabled the 73M2901CL will go into a power saving
mode when idle. The oscillator will be running,
clocks will be supplied to the UART, timers and
interrupt blocks,
Page: 2 of 18
©
2005 TERIDIAN Semiconductor Corporation
Rev 2.0
73M2901CL
V.22bis Single Chip Modem
DATA SHEET
SPECIFYING A CRYSTAL
The manufacturer of a crystal resonator verifies its
frequency of oscillation in a test set-up, but to
ensure that the same frequency is obtained in the
application, the circuit conditions must be the same.
The TERIDIAN 73M2901CL modem requires a
parallel mode (anti-resonant) crystal, the important
specifications of which are as follows:
Mode: Parallel (anti-resonant)
Frequency:11.0592 MHz
Frequency tolerance: ±50 ppm at initial temperature.
Temp. drift: An additional ±50 ppm over full range.
Load capacitance: 18pF or 20pF
ESR: 5Ω max.
Drive level: Less than 1mW.
The peak voltage level of the oscillator should be
checked to assure it will not violate the maximum
voltage levels allowed on the oscillator pins. A
resistor in series with the crystal can be used, if
necessary, to reduce the oscillator’s peak voltage
levels.
Crystals with low ESRs may oscillate at higher than
specified voltage levels.
RESET
A reset is accomplished by holding the RESET pin
high. To ensure a proper power-on reset, the reset
pin must be held high for a minimum of 3µs. At
power on, the voltage at VPD, VPA, and RESET
must come up at the same time for a proper reset.
The signals
DCD, CTS
and
DSR
will be held inactive
for 25ms, acknowledging the reset operation, within
a 250ms time window after the reset-triggering
event. The 73M2901CL is ready for operation after
that 250ms window and/or after the signals
DCD,
CTS
and
DSR
become active.
ASYNCHRONOUS AND SYNCHRONOUS SERIAL
DATA INTERFACE
The serial data interface consists of the TXD and
RXD data paths (LSB shifted in and out first,
respectively); and the TXCLK and RXCLK serial
clock outputs associated with the data pins;
CTS/RTS
flow control;
DCD, DSR
and
DTR.
In
synchronous mode, the data is passed at the bit rate
(tolerance is +1%, -2.5%).
PIN DESCRIPTIONS
POWER PIN DESCRIPTION
PIN
NAME
VPA
VNA
VPD
VND
32 pin
PLCC
15
21
6, 25, 29
5, 22, 26
32 pin
TQFP
10
16
2, 20, 25
1, 17, 22
44 pin LQFP
16
22
2, 12, 27, 33
11, 24, 44, 28
TYPE
I
I
I
I
DESCRIPTION
Positive analog voltage (Analog supply)
Negative analog voltage (Analog ground)
Positive digital voltage (Digital supply)
Negative digital voltage (Digital ground)
ANALOG INTERFACE PIN DESCRIPTION
PIN
NAME
RXA
TXAN
TXAP
VBG
VREF
32 pin
PLCC
20
16
17
19
18
32 pin
TQFP
15
11
12
14
13
44 pin LQFP
21
17
18
20
19
TYPE
I
O
O
O
O
DESCRIPTION
Receive Analog input
Transmit Analog - output
Transmit Analog + output
Analog Band Gap voltage reference (0.1µF to
VNA). This pin must not be connected to external
circuitry other than the decoupling capacitor.
Analog reference voltage (0.1µF to VNA)
Page: 3 of 18
©
2005 TERIDIAN Semiconductor Corporation
Rev 2.0
73M2901CL
V.22bis Single Chip Modem
DATA SHEET
DIGITAL INTERFACE PIN DESCRIPTION
PIN
NAME
RESET
RXCLK
TXCLK
TXD
RXD
USR10
32 pin
PLCC
13
31
28
27
30
12
32 pin
TQFP
9
27
24
23
26
8
44 pin LQFP
9
36
31
30
35
8
TYPE
I
O
O
I
O
I/O
DESCRIPTION
Reset
Receive data synchronous clock
Transmit data synchronous clock
Serial data input from DTE
Serial output to DTE
Programmable I/O port. This pin optionally may
be used to control an external switch for external
Line In Use circuitry.
Programmable I/O port. This pin can optionally be
used to control an external switch for caller ID
operation.
Request to send
Clear to send
Data set ready
Data carrier detect
Ring indicator
Relay driver output
Programmable I/O port
USR11
RTS
CTS
DSR
DCD
RI
RELAY
USR20
11
10
9
8
7
4
3
1
7
6
5
4
3
32
31
29
7
6
5
4
3
43
40
38
I/O
I
O
O
O
O
O
I/O
EXTERNAL INTERRUPTS PIN DESCRIPTION
PIN
NAME
RING
DTR
32 pin
PLCC
2
32
32 pin
TQFP
30
28
44 pin LQFP
39
37
TYPE
I
I
DESCRIPTION
External interrupt – Line interface ring detection
circuitry input
External interrupt – DTE DTR signal input
OSCILLATOR PIN DESCRIPTION
PIN
NAME
OSCIN
OSCOUT
32 pin
PLCC
24
23
32 pin
TQFP
19
18
44 pin LQFP
26
25
TYPE
I
O
DESCRIPTION
Crystal input for internal oscillator, also input for
external source
Crystal oscillator output
Page: 4 of 18
©
2005 TERIDIAN Semiconductor Corporation
Rev 2.0
73M2901CL
V.22bis Single Chip Modem
DATA SHEET
ELECTRICAL SPECIFICATIONS
ABSOLUTE MAXIMUM RATINGS
PARAMETER
Supply Voltage
Pin Input Voltage (except OSCIN)
Pin Input Voltage (OSCIN)
Storage Temperature
RATING
-0.5V to +4.0V
-0.5V to + 6.0V
-0.5V to VPD + 0.5V
-55ºC to 150ºC
NOTE: This is a stress rating only and functional operation of the device at these or any other conditions above those indicated in the operation sections
of this specification is not implied. Exposure to absolute maximum conditions for extended periods of time may affect reliability.
RECOMMENDED OPERATING CONDITIONS
PARAMETER
Supply Voltage
Oscillator Frequency
Operating Temperature
RECEIVER
PARAMETER
Carrier detect On
Carrier detect Off
Carrier Detect Hysteresis
Receive Level
Idle channel noise
Input impedance
Receive Gain Boost
Max Input Level at RxA
Total Harmonic Distortion
(THD)
CONDITIONS
Tip and Ring
Tip and Ring
Tip and Ring
Tip and Ring
0.2KHz – 4.0KHz
RXA
SFR 96.2h = 1
Vref=1.25V
1KHz 450mVpk on RXA
THD=2
nd
RATING
2.7V – 3.6V
11.0592MHz +/- 50ppm
-40ºC to 85ºC
MIN
-43
-48
NOM
MAX
UNIT
dBm0
*
dBm0
*
2
-43
-70
150
18.8
0.587
rd
dB
-9
-65
19.8
0.658
-50
dBm0
*
dB
kΩ
dB
Vpk
dB
19.3
0.622
-70
and 3 harmonic
*
dBm0 refers to the TERIDIAN recommended line interface (8dB loss from transmit pins to the line and 5dB loss from the line to the receiver pin).
Results may vary depending on the selected DAA components. 0dBm=0.775mV
rms
; dBm=10log(V
rms2
/(1mW)(600Ω))
©
2005 TERIDIAN Semiconductor Corporation
Page: 5 of 18
Rev 2.0
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