FUJITSU SEMICONDUCTOR
DATA SHEET
ADVANCED INFO.
AE0.1E
MEMORY
CMOS
4
×
512 K
×
32 BIT
SYNCHRONOUS DYNAMIC RAM
MB81F643242C-60/-70/-10
CMOS 4-Bank
×
524,288-Word
×
32 Bit
Synchronous Dynamic Random Access Memory
s
DESCRIPTION
The Fujitsu MB81F643242C is a CMOS Synchronous Dynamic Random Access Memory (SDRAM) containing
67,108,864 memory cells accessible in a 32-bit format. The MB81F643242C features a fully synchronous
operation referenced to a positive edge clock whereby all operations are synchronized at a clock input which
enables high performance and simple user interface coexistence. The MB81F643242C SDRAM is designed to
reduce the complexity of using a standard dynamic RAM (DRAM) which requires many control signal timing
constraints, and may improve data bandwidth of memory as much as 5 times more than a conventional DRAM.
The MB81F643242C is ideally suited for workstations, personal computers, laser printers, high resolution graphic
adapters/accelerators and other applications where an extremely large memory and bandwidth are required and
where a simple interface is needed.
s
PRODUCT LINE & FEATURES
Parameter
CL - t
RCD
- t
RP
Clock Frequency
Burst Mode Cycle Time
Access Time from Clock
CL = 2
CL = 3
CL = 2
CL = 3
CL = 2
CL = 3
MB81F643242C
-60
2 - 2 - 2 clk min.
3 - 3 - 3 clk min.
167 MHz max.
10 ns min.
6 ns min.
6 ns max.
5.5 ns max.
165 mA max.
-70
-10
2 - 2 - 2 clk min.
2 - 2 - 2 clk min.
3 - 3 - 3 clk min.
3 - 3 - 3 clk min.
143 MHz max.
100 MHz max.
10 ns min.
15 ns min.
7 ns min.
10 ns min.
6 ns max.
7 ns max.
5.5 ns max.
7 ns max.
155 mA max.
115 mA max.
2 mA max.
2 mA max.
Reference
Value@ 67 MHz,
CL=3
2 - 2 - 2 clk min.
3 - 3 - 3 clk min.
67 MHz max.
20 ns min.
15 ns min.
7 ns max.
7 ns max.
100 mA max.
Operating Current
Power Down Mode Current (I
CC2P
)
Self Refresh Current (I
CC6
)
•
•
•
•
•
Single +3.3 V Supply ±0.3 V tolerance
LVTTL compatible I/O interface
4 K refresh cycles every 64 ms
Four bank operation
Burst read/write operation and burst
read/single write operation capability
• Programmable burst type, burst length, and
CAS latency
• Auto-and Self-refresh (every 15.6
µs)
• CKE power down mode
• Output Enable and Input Data Mask
MB81F643242C-60/-70/-10
Advanced Info (AE0.1E)
Pin Number
1, 3, 9, 15, 29, 35, 41, 43, 49, 55, 75, 81
2, 4, 5, 7, 8, 10, 11, 13, 31, 33, 34, 36, 37,
39, 40, 42, 45, 47, 48, 50, 51, 53, 54, 56,
74, 76, 77, 79, 80, 82, 83, 85
6, 12, 32, 38, 44, 46, 52, 58, 72, 78, 84, 86
14, 21, 30, 57, 69, 70, 73
17
18
19
20
22, 23
24
24, 25, 26, 27, 60, 61, 62, 63, 64, 65, 66
67
68
16, 28, 59, 71
Symbol
V
CC
, V
CCQ
DQ
0
to DQ
31
V
SS
, V
SSQ
N.C.
WE
CAS
RAS
CS
BA
1
, BA
0
AP
A
0
to A
10
CKE
CLK
DQM
0
to DQM
3
Supply Voltage
Data I/O
Ground
No Connection
Write Enable
Function
Column Address Strobe
Row Address Strobe
Chip Select
Bank Select (Bank Address)
Auto Precharge Enable
Address Input
Clock Enable
Clock Input
Input Mask/Output Enable
• Row: A
0
to A
10
• Column: A
0
to A
7
4
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