SPANSION MCP
Data Sheet
TM
September 2003
TM
This document specifies SPANSION memory products that are now offered by both Advanced Micro Devices and
Fujitsu. Although the document is marked with the name of the company that originally developed the specification,
these products will be offered to customers of both AMD and Fujitsu.
Continuity of Specifications
There is no change to this datasheet as a result of offering the device as a SPANSION
revisions will occur when appropriate, and changes will be noted in a revision summary.
TM
product. Future routine
Continuity of Ordering Part Numbers
AMD and Fujitsu continue to support existing part numbers beginning with "Am" and "MBM". To order these
products, please use only the Ordering Part Numbers listed in this document.
For More Information
Please contact your local AMD or Fujitsu sales office for additional information about SPANSION
solutions.
TM
memory
FUJITSU SEMICONDUCTOR
DATA SHEET
DS05-50222-1E
Stacked MCP (Multi-Chip Package) FLASH MEMORY & SRAM
CMOS
64M (×16) FLASH MEMORY &
8M (×16) SRAM
MB84SD23280FA/MB84SD23280FE
-70
s
FEATURES
• Power supply voltage of 1.65 V to 1.95 V
• High performance
70 ns maximum access time (Flash)
70 ns maximum access time (SRAM)
• Operating Temperature
–30
°C
to +85
°C
• Package 73-ball FBGA
(Continued)
s
PRODUCT LINEUP
Flash Memory
Supply Voltage (V)
Max Address Access Time (ns)
Max CE Access Time (ns)
Max OE Access Time (ns)
V
CC
f* = 1.8 V
70
70
20
+0.15V
–0.15 V
SRAM
V
CC
s* = 1.8 V
70
70
35
+0.15V
–0.15 V
*: Both V
CC
f and V
CC
s must be in recommended operation range when either part is being accessed.
s
PACKAGE
73-ball plastic FBGA
(BGA-73P-M03)
MB84SD23280FA/MB84SD23280FE
-70
(Continued)
•
FLASH MEMORY
• 0.17
µ
m process technology
• Simultaneous Read/Write operation (Dual Bank)
• FlexBank
TM
*
1
Bank A: 16M bit (16KB
×
4 and 64KB
×
31)
Bank B: 16M bit (64KB
×
32)
Bank C: 16M bit (64KB
×
32)
Bank D: 16M bit (16KB
×
4 and 64KB
×
31)
• Minimum 100,000 program/erase cycles
• Sector Erase Architecture
Four 8K words, a hundred twenty-eight 32K words sectors.
Any combination of sectors can be concurrently erased. Also supports full chip erase.
• WP Input Pin
At V
IL
, allows protection of all sectors, regardless of sector protection/unprotection status
At V
IH
, allows removal of sector protection
• Embedded Erase
TM
*
2
Algorithms
Automatically preprograms and erases the chip or any sector
• Embedded Program
TM
*
2
Algorithms
Automatically writes and verifies data at specified address
• Data Polling and Toggle Bit feature for detection of program or erase cycle completion
• Automatic sleep mode
When address remain stable, the device automatically switches itself to low power mode
• Low V
CC
write inhibit
• Erase Suspend/Resume
Suspends the erase operation to allow a read data and/or program in another sector within the same device
resumes the erase operation
• Sector Protection
Software command sector locking
• Please Refer to “MBM29BS64LF” Datasheet in Detailed Function
•
SRAM
• Power Dissipation
Operating : 50 mA Max
Standby :15
µA
Max
• Power Down Features using CE1s and CE2s
• Data Retention Supply Voltage: 1.0 V to 1.95 V
• CE1s and CE2s Chip Select
• Byte Data Control: LB (DQ
7
to DQ
0
), UB (DQ
15
to DQ
8
)
*1: FlexBank
TM
is a trademark of Fujitsu Limited, Japan.
*2: Embedded Erase
TM
and Embedded Program
TM
are trademarks of Advanced Micro Devices, Inc.
2
MB84SD23280FA/MB84SD23280FE
-70
s
PIN ASSIGNMENT
FBGA
(TOP VIEW)
Marking Side
A10
N.C.
B10
N.C.
D9
A15
C8
A11
C7
A8
B6
N.C.
B5
N.C.
C6
WE
C5
WP
C4
LB
C3
A7
D8
A12
D7
A19
D6
CE2s
D5
RESET
D4
UB
D3
A6
D2
A3
E9
A21
E8
A13
E7
A9
E6
A20
E5
RDY
E4
A18
E3
A5
E2
A2
F10
N.C.
F9
N.C.
F8
A14
F7
A10
G10
N.C.
G9
A16
G8
N.C.
G7
DQ6
H9
N.C.
H8
DQ15
H7
DQ13
H6
DQ4
H5
DQ3
J9
VSS
J8
DQ7
J7
DQ12
J6
VCCs
J5
VCCf
J4
DQ10
J3
DQ0
J2
CE1s
K8
DQ14
K7
DQ5
K6
N.C.
K5
DQ11
K4
DQ2
K3
DQ8
L10
N.C.
M10
N.C.
L6
N.C.
L5
N.C.
F4
A17
F3
A4
F2
A1
F1
N.C.
G4
DQ1
G3
VSS
G2
A0
G1
N.C.
H4
DQ9
H3
OE
H2
CEf
A1
N.C.
B1
N.C.
C1
N.C.
L1
N.C.
M1
N.C.
(BGA-73P-M03)
3
MB84SD23280FA/MB84SD23280FE
-70
s
PIN DESCRIPTION
Pin Configuration
Pin Name
A
18
to A
0
A
21
, A
20
, A
19
DQ
15
to DQ
0
CEf
CE1s
CE2s
OE
WE
RDY
UB
LB
RESET
WP
N.C.
V
SS
V
CC
f
V
CC
s
Address Inputs (Common)
Address Inputs (Flash)
Data Inputs/Outputs (Common)
Chip Enable (Flash)
Chip Enable (SRAM)
Chip Enable (SRAM)
Output Enable (Common)
Write Enable (Common)
Ready Outputs (Flash) Open Drain Output
Upper Byte Control (SRAM)
Lower Byte Control (SRAM)
Hardware Reset Pin (Flash)
Write Protect (Flash)
No Internal Connection
Device Ground (Common)
Device Power Supply (Flash)
Device Power Supply (SRAM)
Function
Input/Output
I
I
I/O
I
I
I
I
I
O
I
I
I
I
Power
Power
Power
s
BLOCK DIAGRAM
V
CC
f
A
21
to A
0
A
21
to A
0
WP
V
SS
RDY
RESET
CEf
64 M bit
Flash Memory
DQ
15
to DQ
0
DQ
15
to DQ
0
V
CC
s
A
18
to A
0
DQ
15
to DQ
0
V
SS
LB
UB
WE
OE
CE1s
CE2s
8 M bit
SRAM
4
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