FUJITSU SEMICONDUCTOR
DATA SHEET
DS05-50102-2E
MCP (Multi-Chip Package) FLASH MEMORY
CMOS
8M (× 8/× 16) FLASH MEMORY &
8M (× 8/× 16) FLASH MEMORY
MB84VB2000
-10
/MB84VB2001
-10
s
FEATURES
• Contain 2 chips of MBM29LV800A, and each chip have separate CE.
• Power supply voltage of 2.7 to 3.6 V
• High performance
100 ns maximum access time
• Operating Temperature
–40 to +85°C
• Minimum 100,000 write/erase cycles
• Sector erase architecture
One 16 K byte, two 8 K bytes, one 32 K byte, and fifteen 64 K bytes
×
2 chips
Any combination of sectors can be concurrently erased. Also supports full chip erase.
• Boot Code Sector Architecture
MB84VB2000: Top sector
MB84VB2001: Bottom sector
• Embedded Erase
TM
Algorithms
Automatically pre-programs and erases the chip or any sector
• Embedded Program
TM
Algorithms
Automatically writes and verifies data at specified address
• Data Polling and Toggle Bit feature for detection of program or erase cycle completion
• Ready/Busy output (RY/BY)
Hardware method for detection of program or erase cycle completion
• Automatic sleep mode
When addresses remain stable, automatically switch themselves to low power mode.
• Low V
CC
write inhibit
≤
2.5 V
• Erase Suspend/Resume
Suspends the erase operation to allow a read data in another sector within the same device
• Please refer to "MBM29LV800TA/BA" data sheet in detailed function
Embedded Erase
TM
and Embedded Program
TM
are trademarks of Advanced Micro Devices, Inc.
MB84VB2000
-10
/MB84VB2001
-10
s
CONNECTION DIAGRAM
(Top View)
A
6
5
4
3
2
1
N.C.
A
10
OE
A
11
A
13
WE
B
V
SS
DQ
5
DQ
7
A
8
A
17
N.C.
C
DQ
1
DQ
2
DQ
4
A
5
CE
2
A
16
D
A
1
A
0
DQ
0
DQ
8
CE
1
V
SS
E
A
2
A
3
A
6
DQ
3
DQ
10
DQ
9
F
A
4
A
7
A
18
DQ
12
V
CC
DQ
11
G
N.C.
RY/BY
RESET
A
12
DQ
6
DQ
13
H
A
9
A
14
A
15
BYTE
DQ
15
/A
-1
DQ
14
Table 1 MB84VB2000/MB84VB2001 Pin Configuration
Pin
A
-1
, A
0
to A
18
DQ
0
to DQ
15
CE
1
CE
2
OE
WE
RY/BY
RESET
BYTE
N.C.
V
SS
V
CC
Function
Address Inputs (Common)
Data Inputs/Outputs (Common)
Chip Enable 1
Chip Enable 2
Output Enable (Common)
Write Enable (Common)
Ready/Busy Outputs (Common)
Hardware Reset Pin/Sector Protection Unlock (Common)
Selects 8-bit or 16-bit mode (Common)
No Internal Connection
Device Ground (Common)
Device Power Supply (Common)
Input/
Output
I
I/O
I
I
I
I
O
I
I
—
Power
Power
3
MB84VB2000
-10
/MB84VB2001
-10
s
PRODUCT LINE UP
Part No.
Ordering Part No.
V
CC
= 3.0 V
+0.6 V
–0.3 V
MB84VB2000/MB84VB2001
-10
100
100
40
Max. Address Access Time (ns)
Max. CE Access Time (ns)
Max. OE Access Time (ns)
s
LOGIC SYMBOL
Table 2
Operation (5)
Auto-Select Manufacture’s Code (1)
L
H
Auto-Select Device Code (1)
L
H
Read (3)
L
Full Standby
Output Disable
Write (Program/Erase)
L
H
Enable Sector Protection (2), (4)
L
H
Verify Sector Protection (2), (4)
L
Temporary Sector Unprotection
Reset (Hardware)/Standby
X
X
H
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
HIGH-Z
V
ID
L
H
L
L
H
L
H
L
V
ID
Code
H
H
L
V
ID
L
H
L
V
ID
X
H
H
X
H
H
H
X
L
H
L
A
0
A
1
A
6
A
9
D
IN
H
X
H
X
H
X
X
X
X
X
X
X
X
HIGH-Z
HIGH-Z
H
H
H
L
L
H
A
0
A
1
A
6
A
9
D
OUT
H
H
L
L
H
H
L
L
V
ID
Code
H
MB84VB2000/MB84VB2001 User Bus Operations (BYTE = V
IH
)
CE
1
H
CE
2
L
L
H
L
L
L
V
ID
Code
H
OE
WE
A
0
A
1
A
6
A
9
DQ
0
to DQ
15
RESET
4
MB84VB2000
-10
/MB84VB2001
-10
Table 3
Operation (5)
Auto-Select Manufacture’s
Code (1)
Auto-Select Device Code (1)
L
H
Read (3)
L
Full Standby
Output Disable
Write (Program/Erase)
L
Enable Sector Protection
(2), (4)
Verify Sector Protection
(2), (4)
Temporary Sector
Unprotection
Reset (Hardware)/Standby
H
L
H
L
X
X
H
L
V
ID
H
L
L
H
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
HIGH-Z
V
ID
L
H
L
L
H
L
V
ID
Code
H
L
L
H
L
V
ID
X
H
H
X
H
H
H
X
L
H
L
A
-1
A
0
A
1
A
6
A
9
D
IN
H
X
H
X
H
X
X
X
X
X
X
X
X
X
X
HIGH-Z
HIGH-Z
H
H
H
L
L
H
A
-1
A
0
A
1
A
6
A
9
D
OUT
H
MB84VB2000/MB84VB2001 User Bus Operations (BYTE = V
IL
)
CE
1
H
L
H
CE
2
L
L
H
L
L
H
L
H
L
L
V
ID
Code
H
H
L
L
L
L
V
ID
Code
H
OE
WE
DQ
15
/
A
-1
A
0
A
1
A
6
A
9
DQ
0
to
DQ
7
RESET
Legend:
L = V
IL
, H = V
IH
, X = V
IL
or V
IH
,
= Pulse input. See DC Characteristics for voltage levels.
Notes:
1.Manufacturer and device codes may also be accessed via a command register write sequence. See
Table 7.
2.Refer to the section on Sector Protection.
3.WE can be V
IL
if OE is V
IL
, OE at V
IH
initiates the write operations.
4.V
CC
= 3.3 V
±10%
5.Do not apply CE
1
= CE
2
= V
IL
at a time.
5
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