FUJITSU SEMICONDUCTOR
DATA SHEET
DS05-50110-1E
MCP (Multi-Chip Package) FLASH MEMORY & SRAM
CMOS
8M (× 8/× 16) FLASH MEMORY &
2M (× 8) STATIC RAM
MB84VD2002
-10
/MB84VD2003
-10
s
FEATURES
• Power supply voltage of 2.7 to 3.6 V
• High performance
100 ns maximum access time
• Operating Temperature
–20 to +85°C
— FLASH MEMORY
• Simultaneous operations Read-while Erase or Read-while-Program
• Minimum 100,000 write/erase cycles
• Sector erase architecture
Two 16 K byte, four 8 K bytes, two 32 K byte, and fourteen 64 K bytes.
Any combination of sectors can be concurrently erased. Also supports full chip erase.
• Boot Code Sector Architecture
MB84VD2002: Top sector
MB84VD2003: Bottom sector
• Embedded Erase
TM
Algorithms
Automatically pre-programs and erases the chip or any sector
• Embedded Program
TM
Algorithms
Automatically writes and verifies data at specified address
• Data Polling and Toggle Bit feature for detection of program or erase cycle completion
• Ready-Busy output (RY/BY)
Hardware method for detection of program or erase cycle completion
• Automatic sleep mode
When addresses remain stable, automatically switch themselves to low power mode.
• Low V
CC
write inhibit
≤
2.5 V
• Erase Suspend/Resume
Suspends the erase operation to allow a read in another sector within the same device
• Please refer to "MBM29DL800TA/BA" data sheet in detailed function
— SRAM
• Power dissipation
Operating : 35 mA max.
Standby : 50
µA
max.
• Power down features using CE1s and CE2s
• Data retention supply voltage: 2.0 V to 3.6 V
Embedded Erase
TM
and Embedded Program
TM
are trademarks of Advanced Micro Devices, Inc.
MB84VD2002
-10
/MB84VD2003
-10
s
PIN ASSIGNMENTS
(Top View)
A
6
5
4
3
2
1
CE1s
A
10
OE
A
11
A
13
WE
B
V
SS
DQ
5
DQ
7
A
8
A
17
V
CC
s
C
DQ
1
DQ
2
DQ
4
A
5
SA*
A
16
D
A
1
A
0
DQ
0
DQ
8
CEf
V
SS
E
A
2
A
3
A
6
DQ
3
DQ
10
DQ
9
F
A
4
A
7
A
18
DQ
12
V
CC
f
DQ
11
G
CE2s
RY/BY
RESET
A
12
DQ
6
DQ
13
H
A
9
A
14
A
15
BYTE
DQ
15
/A
-1
DQ
14
*:
A
17
for SRAM
Table 1 Pin Configuration
Pin
A
0
to A
16
A
-1
, A
17
to A
18
SA
DQ
0
to DQ
7
DQ
8
to DQ
15
CEf
CE1s
CE2s
OE
WE
RY/BY
BYTE
RESET
N.C.
V
SS
V
CC
f
V
CC
s
Function
Address Inputs (Common)
Address Input (Flash)
Address Input (SRAM)
Data Inputs/Outputs (Common)
Data Inputs/Outputs (Flash)
Chip Enable (Flash)
Chip Enable (SRAM)
Chip Enable (SRAM)
Output Enable (Common)
Write Enable (Common)
Ready/Busy Outputs (Flash)
Selects 8-bit or 16-bit mode (Flash)
Hardware Reset Pin/Sector Protection Unlock (Flash)
No Internal Connection
Device Ground (Common)
Device Power Supply (Flash)
Device Power Supply (SRAM)
Input/
Output
I
I
I
I/O
I/O
I
I
I
I
I
O
I
I
—
Power
Power
Power
3
MB84VD2002
-10
/MB84VD2003
-10
s
PRODUCT LINE UP
Flash Memory
Ordering Part No.
V
CC
= 3.0 V
+0.6 V
–0.3 V
SRAM
MB84VD2002-10/MB84VD2003-10
100
100
40
100
100
50
Max. Address Access Time (ns)
Max. CE Access Time (ns)
Max. OE Access Time (ns)
s
BUS OPERATIONS
Table 2 User Bus Operations (BYTE=V
IL
)
Operation (1), (3)
Full Standby
Output Disable
Read from Flash (2)
Write to Flash
Read from SRAM
Write to SRAM
Flash Hardware Reset
CEf
H
X
L
L
H
H
X
CE1s
H
X
X
H
X
H
X
L
L
H
X
CE2s
X
L
X
X
L
X
L
H
H
X
L
OE
X
H
L
H
L
X
X
WE
X
H
H
L
H
L
X
DQ
0
to DQ
7
DQ
8
to DQ
15
HIGH-Z
HIGH-Z
D
OUT
D
IN
D
OUT
D
IN
HIGH-Z
HIGH-Z
HIGH-Z
HIGH-Z
HIGH-Z
HIGH-Z
HIGH-Z
HIGH-Z
RESET
H
H
H
H
H
H
L
Table 3 User Bus Operations (BYTE=V
IH
)
Operation (1), (3)
Full Standby
Output Disable
Read from Flash (2)
CEf
H
X
L
CE1s
H
X
X
H
X
H
X
L
L
H
X
CE2s
X
L
X
X
L
X
L
H
H
X
L
OE
X
H
L
WE
X
H
H
DQ
0
to DQ
7
DQ
8
to DQ
15
HIGH-Z
HIGH-Z
D
OUT
HIGH-Z
HIGH-Z
D
OUT
RESET
H
H
H
Write to Flash
Read from SRAM
Write to SRAM
Flash Hardware Reset
L
H
H
X
H
L
X
X
L
H
L
X
D
IN
D
OUT
D
IN
HIGH-Z
D
IN
HIGH-Z
HIGH-Z
HIGH-Z
H
H
H
L
Legend:
L = V
IL
, H = V
IH
, X = V
IL
or V
IH
. See DC Characteristics for voltage levels.
Notes:
1. Other operations except for indicated this column are inhibited.
2. WE can be V
IL
if OE is V
IL
, OE at V
IH
initiates the write operations.
4. Do not apply CEf = V
IL
, CE1s = V
IL
and CE2s = V
IH
at a time.
4
MB84VD2002
-10
/MB84VD2003
-10
s
FLEXIBLE SECTOR-ERASE ARCHITECTURE on FLASH MEMORY
• Two 16 K byte, four 8 K bytes, two 32 K byte, and fourteen 64 K bytes.
• Individual-sector, multiple-sector, or bulk-erase capability.
(×8)
16K byte/8K word
(×16)
64K byte/32K word
(×8)
(×16)
FFFFFH 7FFFFH
FC000H 7E000H
32K byte/16K word
F4000H 7A000H
8K byte/4K word
F2000H 79000H
8K byte/4K word
Bank 1
8K byte/4K word
EE000H 77000H
8K byte/4K word
EC000H 76000H
32K byte/16K word
E4000H 72000H Bank 2
16K byte/8K word
E0000H 70000H
64K byte/32K word
D0000H 68000H
64K byte/32K word
C0000H 60000H
64K byte/32K word
B0000H 58000H
64K byte/32K word
A0000H 50000H
64K byte/32K word
90000H 48000H
64K byte/32K word
80000H 40000H
64K byte/32K word
Bank 2
64K byte/32K word
60000H 30000H
64K byte/32K word
50000H 28000H
64K byte/32K word
40000H 20000H Bank 1
64K byte/32K word
30000H 18000H
64K byte/32K word
20000H 10000H
64K byte/32K word
10000H 08000H
64K byte/32K word
00000H 00000H
MBM29DL800TA Sector Architecture
MB84VD2002 Sector Architecture
16K byte/8K word
32K byte/16K word
8K byte/4K word
8K byte/4K word
8K byte/4K word
8K byte/4K word
70000H 38000H
32K byte/16K word
16K byte/8K word
64K byte/32K word
64K byte/32K word
64K byte/32K word
64K byte/32K word
64K byte/32K word
64K byte/32K word
64K byte/32K word
64K byte/32K word
64K byte/32K word
F0000H 78000H
64K byte/32K word
64K byte/32K word
64K byte/32K word
64K byte/32K word
FFFFFH 7FFFFH
F0000H 78000H
E0000H 70000H
D0000H 68000H
C0000H 60000H
B0000H 58000H
A0000H 50000H
90000H 48000H
80000H 40000H
70000H 38000H
60000H 30000H
50000H 28000H
40000H 20000H
30000H 18000H
20000H 10000H
1C000H 0C000H
14000H 0A000H
12000H 09000H
10000H 08000H
0E000H 07000H
0C000H 06000H
04000H 02000H
00000H 00000H
MBM29DL800BA Sector Architecture
MB84VD2003 Sector Architecture
5
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