FUJITSU SEMICONDUCTOR
DATA SHEET
DS05-50207-1E
Stacked MCP (Multi-Chip Package) FLASH MEMORY & SRAM
CMOS
32M (× 8/×16) FLASH MEMORY &
8M (× 8/×16) STATIC RAM
MB84VD2228XEA
-90
/MB84VD2229XEA
-90
MB84VD2228XEE
-90
/MB84VD2229XEE
-90
s
FEATURES
• Power supply voltage of 2.7 V to 3.3 V
• High performance
90 ns maximum access time (Flash)
70 ns maximum access time (SRAM)
• Operating Temperature
–25°C to +85°C
• Package 71-ball BGA
(Continued)
s
PRODUCT LINE UP
Flash Memory
Ordering Part No.
V
CC
f, V
CC
s= 3.0V
+0.3 V
–0.3 V
SRAM
MB84VD2228XEA/EE-90/MB84VD2229XEA/EE-90
90
90
40
70
70
35
Max. Address Access Time (ns)
Max. CE Access Time (ns)
Max. OE Access Time (ns)
s
PACKAGE
71-ball plastic FBGA
(BGA-71P-M01)
MB84VD2228XEA/EE/2229XEA/EE
-90
(Continued)
1.FLASH MEMORY
• Simultaneous Read/Write operations (dual bank)
Multiple devices available with different bank sizes
Host system can program or erase in one bank, then immediately and simultaneously read from the other bank
Zero latency between read and write operations
Read-while-erase
Read-while-program
• Minimum 100,000 write/erase cycles
• Sector erase architecture
Eight 4 K words and sixty three 32 K words.
Any combination of sectors can be concurrently erased. Also supports full chip erase.
• Boot Code Sector Architecture
MB84VD2228X: Top sector
MB84VD2229X: Bottom sector
• Embedded Erase
TM
Algorithms
Automatically pre-programs and erases the chip or any sector
• Embedded Program
TM
Algorithms
Automatically writes and verifies data at specified address
• Data Polling and Toggle Bit feature for detection of program or erase cycle completion
• Ready-Busy output (RY/BY)
Hardware method for detection of program or erase cycle completion
• Automatic sleep mode
When addresses remain stable, automatically switch themselves to low power mode.
• Low V
CC
f write inhibit
≤
2.5 V
• Hidden ROM (Hi-ROM) region
64K byte of Hi-ROM, accessible through a new “Hi-ROM Enable” command sequence
Factory serialized and protected to provide a secure electronic serial number (ESN)
• WP/ACC input pin
At V
IL
, allows protection of boot sectors, regardless of sector protection/unprotection status
(MB84VD2228XEA/EE:SA69,SA70 MB84VD2229XEA/EE:SA0,SA1)
At V
IH
, allows removal of boot sector protection
At V
ACC
, program time will reduse by 40%.
• Erase Suspend/Resume
Suspends the erase operation to allow a read in another sector within the same device
• Please refer to “MBM29DL32XTE/BE” data sheet in detailed function
2.SRAM
• Power dissipation
Operating : 50 mA max.
Standby : 25
µA
max.
• Power down features using CE1s and CE2s
• Data retention supply voltage: 1.5 V to 3.3 V
• CE1s and CE2s Chip Select
• Byte data control: LBs (DQ
0
to DQ
7
), UBs (DQ
8
to DQ
15
)
2
MB84VD2228XEA/EE/2229XEA/EE
-90
(Continued)
Pin no.
J2
G3
K3
H4
H5
K6
G6
J7
K2
H3
J3
K4
J6
H6
K7
H7
H1
J1
D5
H2
C5
E4
D3
C3
H8
Pin Name
DQ
0
DQ
1
DQ
2
DQ
3
DQ
4
DQ
5
DQ
6
DQ
7
DQ
8
DQ
9
DQ
10
DQ
11
DQ
12
DQ
13
DQ
14
DQ
15
CEf
CE1s
CE2s
OE
WE
RY/BY
UBs
LBs
CIOf
Chip Enable (Flash)
Chip Enable (SRAM)
Chip Enable (SRAM)
Output Enable (Common)
Write Enable (Common)
Ready/Busy Outputs (Flash) Open Drain Output
Upper Byte Control (SRAM)
Lower Byte Control (SRAM)
I/O Configuration (Flash)
CIOf
=
V
CC
f is Word mode (
×
16),
CIOf
=
V
SS
is Byte mode (
×
8)
I/O Configuration (SRAM)
CIOs
=
V
CC
s is Word mode (
×
16),
CIOs
=
V
SS
is Byte mode (
×
8)
Hardware Reset Pin / Sector Protection Unlock (Flash)
Write Protect / Acceleration (Flash)
I
I
I
I
I
O
I
I
I
Data Inputs / Outputs (Common)
I/O
Function
Input/Output
K5
D4
C4
CIOs
RESET
WP/ACC
I
I
I
(Continued)
5
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