SPANSION MCP
Data Sheet
TM
September 2003
TM
This document specifies SPANSION memory products that are now offered by both Advanced Micro Devices and
Fujitsu. Although the document is marked with the name of the company that originally developed the specification,
these products will be offered to customers of both AMD and Fujitsu.
Continuity of Specifications
There is no change to this datasheet as a result of offering the device as a SPANSION
revisions will occur when appropriate, and changes will be noted in a revision summary.
TM
product. Future routine
Continuity of Ordering Part Numbers
AMD and Fujitsu continue to support existing part numbers beginning with "Am" and "MBM". To order these
products, please use only the Ordering Part Numbers listed in this document.
For More Information
Please contact your local AMD or Fujitsu sales office for additional information about SPANSION
solutions.
TM
memory
FUJITSU SEMICONDUCTOR
DATA SHEET
DS05-50312-1E
Stacked MCP (Multi-Chip Package) FLASH MEMORY & FCRAM
CMOS
64M (×16) FLASH MEMORY &
16M (×16) Mobile FCRAM
TM
MB84VD23381HJ
-70
s
FEATURES
• Power Supply Voltage of 2.7 V to 3.1 V
• High Performance
70 ns maximum random access time (Flash)
60 ns maximum random access time (FCRAM)
• Operating Temperature
–30
°C
to +85
°C
• Package 56-ball BGA
(Continued)
s
PRODUCT LINEUP
Flash
Supply Voltage (V)
Max Random Address Access Time (ns)
Max CE Access Time (ns)
Max OE Access Time (ns)
V
CC
f* = 3.0 V
70
70
30
+0.1 V
–0.3 V
FCRAM
V
CC
r* = 3.0 V
60
60
35
+0.1 V
–0.3 V
* : Both V
CC
f and V
CC
r must be the same level when either part is being accessed.
s
PACKAGE
56-ball plastic FBGA
BGA-56P-M04
MBVD23381HJ-70
(Continued)
— FLASH MEMORY
•
Simultaneous Read/Write operations
(Dual
Bank)
•
FlexBank
TM
*
1
Bank A : 8 Mbit (8 KB
×
8 and 64 KB
×
15)
Bank B : 24 Mbit (64 KB
×
48)
Bank C : 24 Mbit (64 KB
×
48)
Bank D : 8 Mbit (8 KB
×
8 and 64 KB
×
15)
Two virtual Banks are chosen from the combination of four physical banks.
Host system can program or erase in one bank, and then read immediately and simultaneously from the other
bank with zero latency between read and write operations.
Read-while-erase
Read-while-program
•
Minimum 100,000 program/erase cycles
•
Sector erase architecture
Sixteen 4 Kword and one hundred twenty-six 32 Kword sectors in word.
Any combination of sectors can be concurrently erased. It also supports full chip erase.
•
WP/ACC input pin
At V
IL
, allows protection of “outermost” 2 × 8 Kbytes on both ends of boot sectors, regardless of sector
protection/unprotection status
At V
IH
, allows removal of boot sector protection
At V
ACC
, increases program performance
•
Embedded Erase
TM
*
2
Algorithms
Automatically preprograms and erases the chip or any sector
•
Embedded Program
TM
*
2
Algorithms
Automatically writes and verifies data at specified address
•
Ready/Busy output
(RY/BY)
Hardware method for detection of program or erase cycle completion
•
Automatic sleep mode
When addresses remain stable, the device automatically switches itself to low power mode.
•
Low V
CC
f write inhibit
≤
2.5 V
•
Program Suspend/Resume
Suspends the program operation to allow a read in another byte
•
Erase Suspend/Resume
Suspends the erase operation to allow a read data and/or program in another sector within the same device
• Please refer to “MBM29DL64DH“ Datasheet in deteiled function
(Continued)
2
MB84VD23381HJ-70
(Continued)
— FCRAM
TM
*
3
• Power Dissipation
Operating : 20 mA Max
Standby
: 70 µA Max
• Power Down Mode
Sleep
: 10 µA Max
• Power Down Control by CE2r
• Byte Write Control: LB (DQ
7
to DQ
0
), UB (DQ
15
to DQ
8
)
• 8 words Address Access Capability
*1: FlexBank
TM
is a trademark of Fujitsu Limited, Japan.
*2: Embedded Erase
TM
and Embedded Program
TM
are trademarks of Advanced Micro Devices, Inc.
*3: FCRAM
TM
is a trademark of Fujitsu Limited, Japan.
3
MBVD23381HJ-70
s
PIN ASSIGNMENT
(Top View)
Marking Side
B8
A
15
A7
A
11
A6
A
8
A5
WE
A4
B7
A
12
B6
A
19
B5
CE2r
B4
C8
A
21
C7
A
13
C6
A
9
C5
A
20
C4
RY/BY
C3
A
18
C2
A
5
C1
A
2
D8
N.C.
D7
A
14
D6
A
10
E8
A
16
E7
N.C.
E6
DQ
6
F8
N.C.
F7
DQ
15
F6
DQ
13
F5
DQ
4
F4
DQ
3
G8
Vss
G7
DQ
7
G6
DQ
12
G5
Vccr
G4
Vccf
G3
DQ
10
G2
DQ
0
G1
CE1r
H7
DQ
14
H6
DQ
5
H5
N.C.
H4
DQ
11
H3
DQ
2
H2
DQ
8
WP/ACC RESET
A3
LB
A2
A
7
B3
UB
B2
A
6
B1
D3
A
17
D2
A
4
D1
A
1
E3
DQ
1
E2
V
SS
E1
A
0
F3
DQ
9
F2
OE
F1
CEf
INDEX MARK
A
3
(BGA-56P-M04)
4
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