8Mx64 bit SDRAM Unbuffered DIMM F-Series
based on 8Mx8 SDRAM, LVTTL, 2/4-Banks & 4K/8K-Refresh
HYM7V64800/ HYM7V64801/ HYM7V64830/ HYM7V64831
DESCRIPTION
The HYM7V64800/ 64801/ 64830/ 64831 F-Series are high speed 3.3-Volt synchronous dynamic RAM
Modules composed of eight 8Mx8 bit Synchronous DRAMs in 54-pin TSOPII and 8-pin TSSOP 2K bit
E
2
PROM on a 168-pin glass-epoxy printed circuit board. Two 0.22µF and two 0.0022µF decoupling capa-
citors per each SDRAM are mounted on the module.
The HYM7V64800/ 64801/ 64830/ 64831 F-Series are gold plated socket type Dual In-line Memory
Modules suitable for easy interchange and addition of 64M bytes memory. All addresses, data and control
inputs are latched on the rising edge of the master clock input. The data paths are internally pipelined to
achieve very high bandwidths.
FEATURES
•
•
•
•
•
•
168-Pin Unbuffered DIMM
Serial Presence Detect with Serial E
2
PROM
Meets all the other JEDEC specifications
Single 3.3V±0.3V power supply
All device pins are LVTTL compatible
4096 refresh cycles every 64ms or 8192 refresh
cycles every 128ms
•
Fully synchronous ; all inputs referenced to
positive edge of system clock
•
Dual or Quad internal banks with single pulsed
/RAS
•
Auto precharge/precharge all banks by A10 flag
•
Possible to assert random column address
every clock cycle
•
Interleaved auto refresh mode
•
Programmable burst lengths and sequences
- 1,2,4,8,full page for Sequential type
- 1,2,4,8 for Interleave type
•
Programmable /CAS latency ; 1,2,3 clocks
•
Support clock suspend/power down mode by
CKE0
•
Data mask function by DQM
•
Mode register set programming
•
Burst termination command
•
Self refresh provides minimum power, full
internal refresh control
ORDERING INFORMATION
Part No.
HYM7V64800TFG - 10/12/15
HYM7V64801TFG - 10/12/15
HYM7V64830TFG - 10/12/15
HYM7V64831TFG - 10/12/15
Max. Frequency
100/ 83/ 66 MHz
100/ 83/ 66 MHz
100/ 83/ 66 MHz
100/ 83/ 66 MHz
SDRAM Bank
2 Banks
4 Banks
2 Banks
4 Banks
Refresh
4K
4K
8K
8K
Package
TSOP
TSOP
TSOP
TSOP
Plating
Gold
Gold
Gold
Gold
This document is a general product description and is subject to change without notice. Hyundai Electronics does not assume
any responsibility for use of circuits described. No patent licenses are implied.
Sep. 1998
Rev 4.1
HYM7V64800/ HYM7V64801/ HYM7V64830/ HYM7V64831 F-Series
PIN DESCRIPTION
Pin Name
CK0-CK3
Pin Type
INPUT
Description
System Clock Input; All other inputs except CKE are registered
to the SDRAM on the rising edge of CLK.
Clock Enable; Controls internal clock signal and when deactiva-
ted, the SDRAM will be either one of the states among power
down, suspend, or self refresh.
Chip select; Functions command mask(NOP).
Row address strobe; See functional truth table in 8Mx8 Data
Sheets for details.
Column address strobe; See functional truth table in 8Mx8 Data
Sheets for details.
Write Enable; See functional truth table in 8Mx8 Data Sheets for
details.
Data Input / Output Mask
Data Input / Output; Include inputs, outputs, or Hi-z state.
Power Supplies; 3.3V±0.3V
Ground
Serial Address and Data Input / Output.
Serial Clock
Addresses in Serial E
2
PROM for Socket Presence.
CKE0
/S0, /S2
/RAS
/CAS
/WE
DQM0-7
DQ0-DQ63
V
CC
V
SS
SDA
SCL
SA0-SA2
INPUT
INPUT
INPUT
INPUT
INPUT
INPUT
INPUT/
OUTPUT
SUPPLY
SUPPLY
INPUT/
OUTPUT
INPUT
INPUT
HYM7V64800/HYM7V64830 F-Series ( 2Bank 8Mx8 SDRAM Based )
Pin Name
BA0
Pin Type
INPUT
Description
Bank select address inputs; Select one of dual banks during
both /RAS and /CAS activity.
Address Inputs;
A0-A8; X&Y addresses, A0-A13; Opcode for mode register set,
A10; Precharge flag, A9-A12; X addresses only.
A0-A12
INPUT
HYM7V64801/HYM7V64831 F-Series ( 4Bank 8Mx8 SDRAM Based )
Pin Name
BA0, BA1
Pin Type
INPUT
Description
Bank address inputs; Select one of quad banks during both
/RAS and /CAS activity.
Address Inputs;
A0-A8; X&Y addresses, A0-A13; Opcode for mode register set,
A10; Precharge flag, A9-A11; X addresses only.
2
A0-A11
INPUT
Rev 4.1
HYM7V64800/ HYM7V64801/ HYM7V64830/ HYM7V64831 F-Series
PIN NAME
#
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
34
35
36
37
38
39
40
41
42
NAME
Vss
DQ0
DQ1
DQ2
DQ3
Vcc
DQ4
DQ5
DQ6
DQ7
DQ8
Vss
DQ9
DQ10
DQ11
DQ12
DQ13
Vcc
DQ14
DQ15
NC
NC
Vss
NC
NC
Vcc
/WE
DQM0
DQM1
/S0
DU
Vss
A0
A2
A4
A6
A8
A10(AP)
* BA1
Vcc
Vcc
CK0
#
43
44
45
46
47
48
49
50
51
52
53
54
55
56
57
58
59
60
61
62
63
64
65
66
67
68
69
70
71
72
73
74
75
76
77
78
79
80
81
82
83
84
NAME
Vss
DU
/S2
DQM2
DQM3
DU
Vcc
NC
NC
NC
NC
Vss
DQ16
DQ17
DQ18
DQ19
Vcc
DQ20
NC
V
REF
, NC
NC
Vss
DQ21
DQ22
DQ23
Vss
DQ24
DQ25
DQ26
DQ27
Vcc
DQ28
DQ29
DQ30
DQ31
Vss
*CK2
NC
NC
SDA
SCL
Vcc
#
85
86
87
88
89
90
91
92
93
94
95
96
97
98
99
100
101
102
103
104
105
106
107
108
109
110
111
112
113
114
115
116
117
118
119
120
121
122
123
124
125
126
NAME
Vss
DQ32
DQ33
DQ34
DQ35
Vcc
DQ36
DQ37
DQ38
DQ39
DQ40
Vss
DQ41
DQ42
DQ43
DQ44
DQ45
Vcc
DQ46
DQ47
NC
NC
Vss
NC
NC
Vcc
/CAS
DQM4
DQM5
NC
/RAS
Vss
A1
A3
A5
A7
A9
BA0
A11
Vcc
CK1
* A12
#
127
128
129
130
131
132
133
134
135
136
137
138
139
140
141
142
143
144
145
146
147
148
149
150
151
152
153
154
155
156
157
158
159
160
161
162
163
164
165
166
167
168
NAME
Vss
CKE0
NC
DQM6
DQM7
NC
Vcc
NC
NC
NC
NC
Vss
DQ48
DQ49
DQ50
DQ51
Vcc
DQ52
NC
V
REF
, NC
NC
Vss
DQ53
DQ54
DQ55
Vss
DQ56
DQ57
DQ58
DQ59
Vcc
DQ60
DQ61
DQ62
DQ63
Vss
*CK3
NC
SA0
SA1
SA2
Vcc
Note : 1. BA1 is used for HYM7V64801/HYM7V64831 F-Series ( 4 Bank 8Mx8 Based )
2. A12 is used for HYM7V64800/HYM7V64830 F-Series ( 2 Bank 8Mx8 Based )
3. CK2 and CK3 are connected with termination R/C ( Refer to the block diagram )
3
Rev 4.1
HYM7V64800/ HYM7V64801/ HYM7V64830/ HYM7V64831 F-Series
BLOCK DIAGRAM
Note : 1. The serial resistor values of DQs are 10 Ohms.
2. The padding capacitance of termination R/C for CK2/3 is 10pF.
Rev 4.1
4
HYM7V64800/ HYM7V64801/ HYM7V64830/ HYM7V64831 F-Series
I-
1
SERIAL PRESENCE DETECT
BYTE NUMBER
FUNCTION DESCRIBED
[ HYM7V64800/HYM7V64830 F-Series; 2 Banks ]
FUNCTION
VALUE
NOTE
BYTE0
BYTE1
BYTE2
BYTE3
BYTE4
BYTE5
BYTE6
BYTE7
BYTE8
BYTE9
# of Bytes Written into Serial Memory
at Module Manufacturer
Total # of Bytes of SPD Memory Device
Fundamental Memory Type
# of Row Addresses on This Assembly
# of Column Addresses on This Assembly
# of Module Banks on This Assembly
Data Width of This Assembly
Data Width of This Assembly(Continued)
Voltage Interface Standard of This Assembly
SDRAM Cycle Time
@ /CAS Latency=3
128 Bytes
256 Bytes
SDRAM
2 Banks; 13
9
1 Bank
64 Bits
-
LVTTL
t
CLK
(A) 10ns
(B) 12ns
(C) 15ns
t
AC
(A) 8ns
(B) 9ns
(C) 10ns
None
15.625µs
/ Self Refresh Supported
80h
08h
04h
0Dh
09h
01h
40h
00h
01h
(A) A0h
(B) C0h
(C) F0h
3
(A) 80h
(B) 90h
(C) A0h
00h
80h
08h
00h
01h
8Fh
02h
07h
01h
01h
00h
06h
3
(A) C0h
(B) F0h
(C) F0h
2
1
3
BYTE10
SDRAM Access Time from Clock
@ /CAS Latency=3, @Cycle Time=10ns
@ /CAS Latency=3, @Cycle Time=12ns
@ /CAS Latency=3, @Cycle Time=15ns
BYTE11
BYTE12
BYTE13
BYTE14
BYTE15
BYTE16
BYTE17
BYTE18
BYTE19
BYTE20
BYTE21
BYTE22
BYTE23
DIMM Configuration Type
Refresh Rate/Type
Primary SDRAM Width
Error Checking SDRAM Width
Minimum Clock Delay Back to Back
Random Column Address
Burst Lengths Supported
# of Banks on SDRAM Device
2 Bank 8Mx8 Based
CAS # Latency
CS # Latency
Write Latency
SDRAM Module Attributes
( Neither Buffered nor Registered )
SDRAM Module Attributes General
( Burst read, Precharge All, Auto Precharge )
SDRAM Cycle Time
@ /CAS Latency=2
x8
None
t
CCD
=1 Latency
1,2,4,8,Full Page
2 Banks
/CAS
Latency=1,2,3
/CS Latency=0
/WE Latency=0
-
-
t
CLK
(A) 12ns
(B) 15ns
(C) 15ns
5
Rev 4.1
FPGA/CPLD
京公网安备 11010802033920号
Copyright © 2005-2026 EEWORLD.com.cn, Inc. All rights reserved
电子工程世界
