DATASHEET
LOW PHASE NOISE ZERO DELAY BUFFER
Description
The ICS571 is a high speed, high output drive, low phase
noise Zero Delay Buffer (ZDB) which integrates IDT’s
proprietary analog/digital Phase Locked Loop (PLL)
techniques. IDT introduced the world standard for these
devices in 1992 with the debut of the AV9170, and updated
that with the ICS570. The ICS571, part of IDT’s
ClockBlocks™ family, was designed to operate at higher
frequencies, with faster rise and fall times, and with lower
phase noise. The zero delay feature means that the rising
edge of the input clock aligns with the rising edges of both
outputs, giving the appearance of no delay through the
device. There are two outputs on the chip, one being a
low-skew divide by two of the other.
The chip is ideal for synchronizing outputs in a large variety
of systems, from personal computers to data
communications to video. By allowing offchip feedback
paths, the ICS571 can eliminate the delay through other
devices. The use of dividers in the feedback path will enable
the part to multiply by more than two.
ICS571
Features
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Packaged in 8-pin SOIC (Pb free available)
Can function as low phase noise x2 multiplier
Low skew outputs. One is ÷2 of other
Input clock frequency up to 160 MHz at 3.3 V
Phase noise of better than -100 dBc/Hz from 1 kHz to 1
MHz offset from carrier
Can recover poor input clock duty cycle
Output clock duty cycle of 45/55 at 3.3 V
High drive strength for >100 MHz outputs
Full CMOS clock swings with 25 mA drive capability at
TTL levels
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Advanced, low power CMOS process
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Operating voltages of 3.0 to 5.5 V
NOTE: EOL for non-green parts to occur on 5/13/10
per PDN U-09-01
Block Diagram
IDT™ / ICS™
LOW PHASE NOISE ZERO DELAY BUFFER
1
ICS571
REV G 092509
ICS571
LOW PHASE NOISE ZERO DELAY BUFFER
ZDB AND MULTIPLIER/DIVIDER
Pin Assignment
Feedback Configuration Table and Frequency Ranges (at 3.3 V)
Feedback From
CLK
CLK/2
CLK
Input clock frequency
2x Input clock frequency
CLK/2
Input clock frequency/2
Input clock frequency
Input Range
20 to 160 MHz
10 to 80 MHz
Pin Descriptions
Pin
Number
1
2
3
4
5
6
7
8
Pin
Name
ICLK
VDD
GND
CLK/2
GND
VDD
CLK
FBIN
Pin
Type
CI
P
P
O
P
P
O
CI
Reference clock input.
Pin Description
Connect to +3.3 V or +5 V. Must be same as other VDD.
Connect to ground.
Clock output per table above. Low skew divide by two of pin 7 clock.
Connect to ground.
Connect to +3.3 V or +5 V. Must be same as other VDD.
Clock output per table above.
Feedback clock input. Connect to CLK or CLK/2 per table above.
Key: CI = clock input; I = input; O = output; P = power supply connection.
IDT™ / ICS™
LOW PHASE NOISE ZERO DELAY BUFFER
2
ICS571
REV G 092509
ICS571
LOW PHASE NOISE ZERO DELAY BUFFER
ZDB AND MULTIPLIER/DIVIDER
External Components
The ICS571 requires a minimum number of external
components for proper operation.
A decoupling capacitor of 0.01µF must be connected
between VDD and GND on each side of the chip (between
pins 2 and 3, and between pins 6 and 5). They must be
connected close to the ICS571 to minimize lead inductance.
No external power supply filtering is required for this device.
A 33Ω terminating resistor can be used next to each output
pin.
Absolute Maximum Ratings
Stresses above the ratings listed below can cause permanent damage to the ICS571. These ratings, which are
standard values for IDT commercially rated parts, are stress ratings only. Functional operation of the device at these
or any other conditions above those indicated in the operational sections of the specifications is not implied.
Exposure to absolute maximum rating conditions for extended periods can affect product reliability. Electrical
parameters are guaranteed only over the recommended operating temperature range.
Item
Supply Voltage, VDD, referenced to GND
Inputs, referenced to GND
Clock Output, referenced to GND
Storage Temperature
Soldering Temperature, max of 10 seconds
Ambient Operating Temperature
7V
Rating
-0.5 V to VDD+0.5 V
-0.5 V to VDD+0.5 V
-65 to +150° C
260° C
0 to +70° C
IDT™ / ICS™
LOW PHASE NOISE ZERO DELAY BUFFER
3
ICS571
REV G 092509
ICS571
LOW PHASE NOISE ZERO DELAY BUFFER
ZDB AND MULTIPLIER/DIVIDER
DC Electrical Characteristics
Unless stated otherwise,
VDD = 5.0 V or 3.3 V,
Ambient Temperature 0 to +70° C
Parameter
Operating Supply Voltage
Input High Voltage
Input Low Voltage
Output High Voltage,
CMOS level
Output High Voltage
Output Low Voltage
IDD Operating Supply
Current, 133 in, 133 out
IDD Operating Supply
Current, 50 in, 100 out
Short Circuit Current
Input Capacitance
Symbol
VDD
V
IH
V
IL
V
OH
V
OH
V
OL
Conditions
ICLK, FBIN (pins 1 and 8)
ICLK, FBIN (pins 1 and 8)
I
OH
= -4 mA
I
OH
= -25 mA
I
OL
= 25 mA
No load, 3.3 V
No load, 3.3 V
Min.
3
VDD/2+1
VDD-0.4
2.4
Typ.
VDD/2
VDD/2
Max.
5.5
VDD/2-1
Units
V
V
V
V
V
0.4
34
26
±100
5
V
mA
mA
mA
pF
I
OS
C
IN
Each output
ICLK, FBIN
IDT™ / ICS™
LOW PHASE NOISE ZERO DELAY BUFFER
4
ICS571
REV G 092509
ICS571
LOW PHASE NOISE ZERO DELAY BUFFER
ZDB AND MULTIPLIER/DIVIDER
AC Electrical Characteristics
Unless stated otherwise,
VDD = 5.0 V or 3.3 V,
Ambient Temperature 0 to +70° C
Parameter
Input Frequency, clock input
Input Frequency, clock input
Skew CLK/2 with respect to CLK
Input clock to output connected to FBIN
Output Clock Rise Time, 5 V
Output Clock Fall Time, 5 V
Output Clock Rise Time, 3.3 V
Output Clock Fall Time, 3.3 V
Input Clock Duty Cycle, 3.3 V
Output Clock Duty Cycle, 3.3 V
Absolute Clock Period Jitter, CLK,
Note 3
One-Sigma Clock Period Jitter, CLK,
Note 3
Phase Noise, Relative to carrier
Phase Noise, Relative to carrier
Symbol
f
IN
f
IN
Conditions
FB from CLK
FB from CLK/2
Note 2
Note 2
0.8 to 2.0 V, 15 pF load
2.0 to 0.8 V, 15 pF load
0.8 to 2.0 V, 15 pF load
2.0 to 0.8 V, 15 pF load
fin = 150 MHz
At VDD/2
Deviation from Mean
Min.
20
10
150
-500
Typ.
Max. Units
160
80
MHz
MHz
ps
ps
ns
ns
ns
ns
80
%
%
ps
ps
dBc/Hz
dBc/Hz
55
500
0.3
0.4
0.45
0.55
850
500
20
45
49 to 51
±80
50
1 kHz offset
100 kHz offset
-105
-115
Notes:
1. Sresses beyond these can permanently damage the device.
2. Assumes clocks with the same rise time, measured from rising edges at VDD/2. Measured with 33Ω termination
resistors and 15 pF loads. Applies to both 3.3 V and 5 V operation.
3. CLK/2 has lower jitter (both absolute and one sigma, in ps) than CLK.
Thermal Characteristics
Parameter
Thermal Resistance Junction to
Ambient
Symbol
θ
JA
θ
JA
θ
JA
θ
JC
Conditions
Still air
1 m/s air flow
3 m/s air flow
Min.
Typ.
Max. Units
°
C/W
°
C/W
°
C/W
°
C/W
Thermal Resistance Junction to Case
IDT™ / ICS™
LOW PHASE NOISE ZERO DELAY BUFFER
5
ICS571
REV G 092509
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