Am29LV116M
Data Sheet
-XO\
7KH IROORZLQJ GRFXPHQW VSHFLILHV 6SDQVLRQ PHPRU\ SURGXFWV WKDW DUH QRZ RIIHUHG E\ ERWK $GYDQFHG
0LFUR 'HYLFHV DQG )XMLWVX $OWKRXJK WKH GRFXPHQW LV PDUNHG ZLWK WKH QDPH RI WKH FRPSDQ\ WKDW RULJ
LQDOO\ GHYHORSHG WKH VSHFLILFDWLRQ WKHVH SURGXFWV ZLOO EH RIIHUHG WR FXVWRPHUV RI ERWK $0' DQG
)XMLWVX
Continuity of Specifications
7KHUH LV QR FKDQJH WR WKLV GDWDVKHHW DV D UHVXOW RI RIIHULQJ WKH GHYLFH DV D 6SDQVLRQ SURGXFW $Q\
FKDQJHV WKDW KDYH EHHQ PDGH DUH WKH UHVXOW RI QRUPDO GDWDVKHHW LPSURYHPHQW DQG DUH QRWHG LQ WKH
GRFXPHQW UHYLVLRQ VXPPDU\ ZKHUH VXSSRUWHG )XWXUH URXWLQH UHYLVLRQV ZLOO RFFXU ZKHQ DSSURSULDWH
DQG FKDQJHV ZLOO EH QRWHG LQ D UHYLVLRQ VXPPDU\
Continuity of Ordering Part Numbers
$0' DQG )XMLWVX FRQWLQXH WR VXSSRUW H[LVWLQJ SDUW QXPEHUV EHJLQQLQJ ZLWK $P DQG 0%0 7R RUGHU
WKHVH SURGXFWV SOHDVH XVH RQO\ WKH 2UGHULQJ 3DUW 1XPEHUV OLVWHG LQ WKLV GRFXPHQW
For More Information
3OHDVH FRQWDFW \RXU ORFDO $0' RU )XMLWVX VDOHV RIILFH IRU DGGLWLRQDO LQIRUPDWLRQ DERXW 6SDQVLRQ
PHPRU\ VROXWLRQV
QiyvphvÃIir
Ã
!%'
à Srvv Ã
6
6rqr Ã
"
à DrÃ9hr Ã
6
vyÃ&Ã!"
PRODUCTION PENDING
Production is subject to customer demand. Contact your
local AMD sales representative for more information
Am29LV116M
16 Megabit (2 M x 8-Bit) MirrorBit
TM
3.0 Volt-only Boot Sector Flash Memory
DISTINCTIVE CHARACTERISTICS
■
Single power supply operation
— 2.7 to 3.6 volt read and write operations for
battery-powered applications
■
Manufactured on 0.23 µm MirrorBit process
technology
— Compatible with and replaces Am29LV116D and
Am29LV116B
■
SecSi
TM
(Secured Silicon) Sector region
— 128-word/256-byte sector for permanent, secure
identification through an 8-word/16-byte random
Electronic Serial Number, accessible through a
command sequence
■
Embedded Algorithms
— Embedded Erase algorithm automatically
preprograms and erases the entire chip or any
combination of designated sectors
— Embedded Program algorithm automatically
writes and verifies data at specified addresses
■
Minimum 100,000 write cycle guarantee
per sector
■
20-year data retention at 125°C
— Reliable operation for the life of the system
■
Package option
— 40-pin TSOP
■
CFI (Common Flash Interface) compliant
— Provides device-specific information to the
system, allowing host software to easily
reconfigure for different Flash devices
■
Compatibility with JEDEC standards
— Pinout and software compatible with single-
power supply Flash
— Superior inadvertent write protection
■
Data# Polling and toggle bits
— Provides a software method of detecting program
or erase operation completion
■
Ready/Busy# pin (RY/BY#)
— Provides a hardware method of detecting
program or erase cycle completion
■
Erase Suspend/Erase Resume
— Suspends an erase operation to read data from,
or program data to, a sector that is not being
erased, then resumes the erase operation
■
Hardware reset pin (RESET#)
— Hardware method to reset the device to reading
array data
—
May be programmed and locked at the factory or by
the customer
■
High performance
— Access times as fast as 70 ns
■
Ultra low power consumption (typical values at
5 MHz)
— 400 nA Automatic Sleep mode current
— 400 nA standby mode current
— 15 mA read current
— 40 mA program/erase current
■
Flexible sector architecture
— One 16 Kbyte, two 8 Kbyte, one 32 Kbyte, and
thirty-one 64 Kbyte sectors
— Supports full chip erase
— Sector Protection features:
A hardware method of locking a sector to prevent
any program or erase operations within that sector
Sectors can be locked in-system or via
programming equipment
Temporary Sector Unprotect feature allows code
changes in previously locked sectors
■
Unlock Bypass Program Command
— Reduces overall programming time when issuing
multiple program command sequences
■
Top or bottom boot block configurations
available
This Data Sheet states AMD’s current technical specifications regarding the Product described herein. This Data
Sheet may be revised by subsequent versions or modifications due to changes in technical specifications.
Publication#
26008
Rev:
A
Amendment/+3
Issue Date:
April 7, 2003
P E N D I N G
GENERAL DESCRIPTION
The Am29LV116M is a 16 Mbit, 3.0 Volt-only Flash
memory organized as 2,097,152 bytes. The device is
offered in a 40-pin TSOP package. The byte-wide (x8)
data appears on DQ7–DQ0. All read, program, and
erase operations are accomplished using only a single
power supply. The device can also be programmed in
standard EPROM programmers.
The standard device offers access times of 70, 90, and
120 ns, allowing high speed microprocessors to
operate without wait states. To eliminate bus conten-
tion the device has separate chip enable (CE#), write
enable (WE#) and output enable (OE#) controls.
The device requires only a
single 3.0 volt power sup-
ply
for both read and write functions. Internally gener-
ated and regulated voltages are provided for the
program and erase operations.
The device is entirely command set compatible with the
JEDEC single-power-supply Flash standard.
Com-
mands are written to the command register using stan-
dard microprocessor write timings. Register contents
serve as input to an internal state-machine that con-
trols the erase and programming circuitry. Write cycles
also internally latch addresses and data needed for the
programming and erase operations. Reading data out
of the device is similar to reading from other Flash or
EPROM devices.
Device programming occurs by executing the program
command sequence. This initiates the
Embedded
Program
algorithm—an internal algorithm that auto-
matically times the program pulse widths and verifies
proper cell margin. The
Unlock Bypass
mode facili-
tates faster programming times by requiring only two
write cycles to program data instead of four.
Device erasure occurs by executing the erase com-
mand sequence. This initiates the
Embedded Erase
algorithm—an internal algorithm that automatically pre-
programs the array (if it is not already programmed) be-
fore executing the erase operation. During erase, the
device automatically times the erase pulse widths and
verifies proper cell margin.
The host system can detect whether a program or
erase operation is complete by observing the RY/BY#
pin, or by reading the DQ7 (Data# Polling) and DQ6
(toggle)
status bits.
After a program or erase cycle
has been completed, the device is ready to read array
data or accept another command.
The
sector erase architecture
allows memory sectors
to be erased and reprogrammed without affecting the
data contents of other sectors. The device is fully
erased when shipped from the factory.
Hardware data protection
measures include a low
V
CC
detector that automatically inhibits write opera-
tions during power transitions. The
hardware sector
protection
feature disables both program and erase
operations in any combination of the sectors of mem-
ory. This can be achieved in-system or via program-
ming equipment.
The
Erase Suspend
feature enables the user to put
erase on hold for any period of time to read data from,
or program data to, any sector that is not selected for
erasure. True background erase can thus be achieved.
The
Program Suspend/Program Resume
feature en-
ables the host system to pause a program operation in
a given sector to read any other sector and then com-
plete the program operation.
The
hardware RESET# pin
terminates any operation
in progress and resets the internal state machine to
reading array data. The RESET# pin may be tied to the
system reset circuitry. A system reset would thus also
reset the device, enabling the system microprocessor
to read the boot-up firmware from the Flash memory.
The device offers two power-saving features. When
addresses have been stable for a specified amount of
time, the device enters the
automatic sleep mode.
The system can also place the device into the
standby
mode.
Power consumption is greatly reduced in both
these modes.
AMD’s MirrorBit flash technology combines years of
Flash memory manufacturing experience to produce
the highest levels of quality, reliability and cost effec-
tiveness. The device electrically erases all bits
within a sector simultaneously via Fowler-Nordheim
tunneling. The data is programmed using hot electron
injection.
2
Am29LV116M
April 7, 2003
P E N D I N G
TABLE OF CONTENTS
Product Selector Guide . . . . . . . . . . . . . . . . . . . . . 4
Connection Diagrams . . . . . . . . . . . . . . . . . . . . . . . 5
Pin Configuration . . . . . . . . . . . . . . . . . . . . . . . . . . 6
Logic Symbol . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6
Ordering Information . . . . . . . . . . . . . . . . . . . . . . . 7
Standard Products .................................................................... 7
Device Bus Operations . . . . . . . . . . . . . . . . . . . . . . 8
Table 1. Am29LV116M Device Bus Operations ................................8
Table 9. Am29LV116M Command Definitions .............................. 25
Write Operation Status . . . . . . . . . . . . . . . . . . . . 26
DQ7: Data# Polling ................................................................. 26
Figure 6. Data# Polling Algorithm .................................................. 26
Requirements for Reading Array Data ..................................... 8
Writing Commands/Command Sequences .............................. 8
Program and Erase Operation Status ...................................... 9
Standby Mode .......................................................................... 9
Automatic Sleep Mode ............................................................. 9
RESET#: Hardware Reset Pin ................................................. 9
Output Disable Mode ................................................................ 9
Table 2. Am29LV116MT Top Boot Sector Address Table ..............10
Table 3. Am29LV116MB Bottom Boot Sector Address Table .........11
RY/BY#: Ready/Busy# ............................................................ 27
DQ6: Toggle Bit I .................................................................... 27
DQ2: Toggle Bit II ................................................................... 27
Reading Toggle Bits DQ6/DQ2 ............................................... 27
DQ5: Exceeded Timing Limits ................................................ 28
DQ3: Sector Erase Timer ....................................................... 28
Figure 7. Toggle Bit Algorithm........................................................ 28
Table 10. Write Operation Status ................................................... 29
Absolute Maximum Ratings . . . . . . . . . . . . . . . . 30
Figure 8. Maximum Negative Overshoot Waveform ...................... 30
Figure 9. Maximum Positive Overshoot Waveform........................ 30
Autoselect Mode ..................................................................... 12
Table 4. Am29LV116M Autoselect Codes (High Voltage Method) .12
Operating Ranges . . . . . . . . . . . . . . . . . . . . . . . . . 30
DC Characteristics . . . . . . . . . . . . . . . . . . . . . . . . 31
CMOS Compatible .................................................................. 31
Test Conditions . . . . . . . . . . . . . . . . . . . . . . . . . . 32
Figure 10. Test Setup..................................................................... 32
Table 11. Test Specifications ......................................................... 32
Sector Protection/Unprotection ............................................... 13
Temporary Sector Unprotect .................................................. 13
Figure 1. Temporary Sector Unprotect Operation........................... 13
Figure 1. In-System Single High Voltage Sector Protect/Unprotect Al-
gorithms .......................................................................................... 14
Key to Switching Waveforms .................................................. 32
Figure 11. Input Waveforms and Measurement Levels ................. 32
SecSi (Secured Silicon) Sector Flash Memory Region .......... 15
Table 1. SecSi Sector Contents ......................................................15
Figure 2. SecSi Sector Protect Verify.............................................. 16
AC Characteristics . . . . . . . . . . . . . . . . . . . . . . . . 33
Read Operations .................................................................... 33
Figure 12. Read Operation Timing................................................. 33
Hardware Reset (RESET#) .................................................... 34
Figure 13. RESET# Timings .......................................................... 34
Hardware Data Protection ...................................................... 16
Low V
CC
Write Inhibit .............................................................. 16
Write Pulse “Glitch” Protection ............................................... 16
Logical Inhibit .......................................................................... 16
Power-Up Write Inhibit ............................................................ 16
Common Flash Memory Interface (CFI) . . . . . . . 16
Table 5. CFI Query Identification String ..........................................17
Table 6. System Interface String .....................................................17
Table 7. Device Geometry Definition ..............................................18
Table 8. Primary Vendor-Specific Extended Query ........................19
Erase/Program Operations ..................................................... 35
Figure 14. Program Operation Timings..........................................
Figure 15. Chip/Sector Erase Operation Timings ..........................
Figure 16. Data# Polling Timings (During Embedded Algorithms).
Figure 17. Toggle Bit Timings (During Embedded Algorithms)......
Figure 18. DQ2 vs. DQ6.................................................................
36
36
37
37
38
Temporary Sector Unprotect .................................................. 38
Figure 19. Temporary Sector Unprotect Timing Diagram .............. 38
Figure 20. Sector Protect/Unprotect Timing Diagram .................... 39
Figure 21. Alternate CE# Controlled Write Operation Timings ...... 41
Command Definitions . . . . . . . . . . . . . . . . . . . . . . 20
Reading Array Data ................................................................ 20
Reset Command ..................................................................... 20
Autoselect Command Sequence ............................................ 20
Byte Program Command Sequence ....................................... 20
Unlock Bypass Command Sequence ..................................... 21
Figure 3. Program Operation .......................................................... 21
Chip Erase Command Sequence ........................................... 22
Sector Erase Command Sequence ........................................ 22
Erase Suspend/Erase Resume Commands ........................... 22
Figure 4. Erase Operation............................................................... 23
Program Suspend/Program Resume Command Sequence ... 24
Figure 5. Program Suspend/Program Resume............................... 24
Erase and Programming Performance . . . . . . . 42
Latchup Characteristics . . . . . . . . . . . . . . . . . . . . 42
TSOP Pin Capacitance . . . . . . . . . . . . . . . . . . . . . 42
Data Retention. . . . . . . . . . . . . . . . . . . . . . . . . . . . 42
Physical Dimensions . . . . . . . . . . . . . . . . . . . . . . 43
TS 040—40-Pin Standard TSOP ............................................ 43
TSR040—40-Pin Reverse TSOP ........................................... 44
Revision Summary . . . . . . . . . . . . . . . . . . . . . . . . 45
Revision A (June 24, 2002) .................................................... 45
Revision A + 1 (July 3, 2002) .................................................. 45
Revision A + 2 (February 6, 2003) .......................................... 45
Revision A + 3 (April 7, 2003) ................................................. 45
Command Definitions ............................................................. 25
April 7, 2003
Am29LV116M
3
P E N D I N G
PRODUCT SELECTOR GUIDE
Family Part Number
Speed Options
Max access time, ns (t
ACC
)
Max CE# access time, ns (t
CE
)
Max OE# access time, ns (t
OE
)
Note:
See “AC Characteristics” for full specifications.
V
CC
= 2.7–3.6 V
V
CC
= 3.0–3.6 V
70
70R
70
70
30
Am29LV116M
90
90R
90
90
35
120
120R
120
120
50
BLOCK DIAGRAM
RY/BY#
V
CC
V
SS
RESET#
Erase Voltage
Generator
Input/Output
Buffers
Sector Switches
DQ0
–
DQ7
WE#
State
Control
Command
Register
PGM Voltage
Generator
Chip Enable
Output Enable
Logic
STB
Data
Latch
CE#
OE#
STB
V
CC
Detector
Timer
Address Latch
Y-Decoder
Y-Gating
X-Decoder
Cell Matrix
A0–A20
4
Am29LV116M
April 7, 2003
京公网安备 11010802033920号
Copyright © 2005-2026 EEWORLD.com.cn, Inc. All rights reserved
电子工程世界
